Reset Flow - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

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12.0 English

The top-level RESET input (example design level) is debounced and connected to the core ( reset_pb ). This signal is aggregated with the serial transceiver reset status and the hot-plug reset from within the core reset logic ( sys_reset_out ) to generate a reset to the core. This signal is expected to connect to the core reset input. The following figure illustrates this behavior.

Figure 3-9: Reset Flow

X-Ref Target - Figure 3-9