For comprehensive information about Vivado simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 14] .
IMPORTANT: For cores targeting 7 series, Zynq-7000, UltraScale and UltraScale+ devices, UNIFAST libraries are not supported. Xilinx IP is tested and qualified with UNISIM libraries only.
The Aurora 64B/66B core provides a demonstration test bench for the example design. Simulation status is reported through messages. The TEST COMPLETED SUCCESSFULLY message signifies the completion of the example design simulation.
Note: The message Reached max. simulation time limit means that simulation was not successful. See Debugging for more information.
Simulating the duplex core is a single-step process after generating the example design. Simplex core simulation requires partner generation. The partner core is generated automatically and the synthesized netlist is available under the simulation file set when clicking Open IP Example Design . Due to the synthesizing of the partner core, opening an example design of a simplex core takes more time than the duplex example design generation.