Timing - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

The following figure shows the timing for the reset signal. In a quiet environment, t CU is generally less than 500 clock cycles. In a noisy environment, t CU can be much longer.

Figure 3-14: Reset and Power Down Timing

X-Ref Target - Figure 3-14

pg074_reset-power-down-timing_x14642.jpg