Top‐Level Interface - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

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12.0 English

The Aurora 64B/66B top-level (block level) file contains the top-level interface definition and is the starting point for a user design. The top-level file instantiates the Aurora 64B/66B lane module, the TX and RX AXI4-Stream modules, the global logic module, and the GTX, GTH or GTY transceiver wrapper. This top-level wrapper file is instantiated in the example design file together with the clock, reset circuit, and frame generator and checker modules.

This Figure shows the Aurora 64B/66B top-level for a duplex configuration.

Figure 2-5: Aurora 64B/66B Duplex Top-Level Architecture

X-Ref Target - Figure 2-5


The timing requirements for the streaming and framing interfaces are described in Framing Interface and Streaming Interface .

This Figure shows an n -byte example of the Aurora 64B/66B AXI4-Stream data interface bit ordering.

Figure 2-6: AXI4-Stream Interface Bit Ordering

X-Ref Target - Figure 2-6