The following figure shows the simplex-TX core and simplex-RX core connected in a system. CONFIG1 and CONFIG2 can be in same or multiple device(s).
Following is the recommended procedure of TX cores reset and RX cores reset assertion in the simplex core (see the following figure).
- The TX cores
reset_pbis asserted for a duration not less than 128*
user_clktime period followed by
reset_pbon the RX simplex core asserted for a duration not less than 128*
rx_channel_upare deasserted after a minimum of five
- The signal
reset_pbin the RX simplex core is deasserted (or) released before
reset_pbis deasserted in the TX simplex core. This sequence occurs because, while the auto simplex recovery feature allows both boards to be brought up independently, this ensures that TX transmits the Aurora 64B/66B initialization sequence when the simplex-RX core is ready.
rx_channel_upis asserted before
tx_channel_upassertion. This condition must be satisfied by the simplex-RX core and the simplex timer parameters (SIMPLEX_TIMER_VALUE) in the simplex-TX core need to be adjusted to meet this criteria. The SIMPLEX_TIMER_VALUE parameter can be updated in
tx_channel_upis asserted after the simplex-TX core completes the Aurora 64B/66B protocol channel initialization sequence transmission for the configured time. Asserting
tx_channel_uplast ensures that the simplex-TX core transmits an Aurora 64B/66B initialization sequence when the simplex-RX core is ready.
- For TX/RX simplex cores, the reset sequence in duplex cores for
pma_initassertions can be followed. However, the SIMPLEX_TIMER_VALUE needs to be tuned based on the use model of the core.