User Flow Control Interface - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

The Aurora 64B/66B protocol includes user flow control (UFC) to allow channel partners to send control information using a separate in-band channel. Applications send short UFC messages to the channel partner without waiting for the frame in progress to end. The higher priority UFC message shares the channel with lower-priority regular frame data. UFC messages are interruptible by high-priority control blocks such as Clock Compensation (CC)/Not Ready Idles (NR)/Channel Bonding (CB)/NFC blocks. UFC message interruption is visible when the UFC option is selected.

This Figure shows the UFC port interface. Table: User Flow Control (UFC) Interface Ports describes the UFC interface ports.

Figure 2-21: UFC Port Interface

X-Ref Target - Figure 2-21

pg074_ufc_port_interface.jpg
Table 2-9: User Flow Control (UFC) Interface Ports

Name

Direction

Clock Domain

Description

UFC_S_AXIS_TX

ufc_tx_req (2)

Input

user_clk

ufc_tx_req indicates a UFC message request to send by the channel partner. After a request, the s_axi_ufc_tx_tdata bus is ready to send data after two cycles unless interrupted by a higher priority event. The

s_axi_ufc_tx_tvalid must be asserted when you want to send a UFC request.

ufc_tx_ms[0:7] or ufc_tx_ms[7:0] (2)

Input

user_clk

Specifies the number of bytes in the UFC message (message size). The maximum UFC

message size is 256 bytes. The value specified is one less than the actual number of bytes transferred (a value of 3 transmits 4 bytes of data).

s_axi_ufc_tx_tready

Output

user_clk

Indicates the Aurora 64B/66B core is ready to accept UFC data on s_axi_ufc_tx_tdata. This signal is asserted two clock cycles after ufc_tx_req when no high-priority requests are in progress. s_axi_ufc_tx_tready continues to be asserted while the core waits for data for the most recently requested UFC message. The signal is deasserted for CC, CB, and NFC requests which are higher priority. While s_axi_ufc_tx_tready is asserted, s_axi_tx_tready is deasserted.

s_axi_ufc_tx_tdata[0:(64 n –1)] or s_axi_ufc_tx_tdata[(64 n –1):0] (1)

Input

user_clk

Input bus for Aurora 64B/66B channel UFC message data. Sampled only if s_axi_ufc_tx_tvalid and s_axi_ufc_tx_tready are asserted. If the number of message bytes is not an integer multiple of the bus width in bytes, the only bytes used are those needed on the last cycle to finish the message starting from the leftmost byte of the bus.

s_axi_ufc_tx_tvalid

Input

user_clk

Indicates valid UFC data on s_axi_ufc_tx_tdata. If deasserted while s_axi_ufc_tx_tready is asserted, Idle blocks are sent in the UFC message.

UFC_M_AXIS_RX

m_axi_ufc_rx_tdata[0:(64 n –1)] or m_axi_ufc_rx_tdata[(64 n –1):0] (1)

Output

user_clk

Incoming UFC message data from the channel partner.

m_axi_ufc_rx_tvalid

Output

user_clk

Indicates valid UFC data on the m_axi_ufc_rx_tdata port. When not asserted, all values on the m_axi_ufc_rx_tdata port should be ignored.

m_axi_ufc_rx_tlast

Output

user_clk

Indicates the end of the incoming UFC message.

m_axi_ufc_rx_tkeep[0:(8 n –1)] or m_axi_ufc_rx_tkeep[(8 n –1):0] (1)

Output

user_clk

Specifies the number of valid data bytes presented on the m_axi_ufc_rx_tdata port on the last word of a UFC message. Valid only when m_axi_ufc_rx_tlast is asserted. Each bit indicates one valid byte. Maximum size of the UFC message is 256 bytes.

ufc_in_progress (3)

Output

user_clk

Specifies the status of the current UFC transmission. This is an active-Low signal. A Low on this port indicates that UFC reception is in progress.

Notes:

1. n is the number of lanes.

2. ufc_tx_req and ufc_tx_ms are available just below the UFC_S_AXIS_TX interface.

3. ufc_in_progres is available just below the UFC_M_AXIS_RX interface.