This appendix provides details about how this IP core was tested for compliance.
Aurora 64B/66B cores are verified for protocol compliance using an array of automated hardware and simulation tests. The core comes with an example design implemented using a linear feedback shift register (LFSR) for understanding and verification of the core features.
Aurora 64B/66B cores are tested in hardware for functionality, performance, and reliability using Xilinx evaluation boards. Aurora 64B/66B verification test suites for all possible modules are continuously being updated to increase test coverage across the range of possible parameters for each individual module.
A series of test scenarios are validated using various Xilinx development boards which are listed in Table: Xilinx Development Boards . These boards can be used to prototype system designs and the core can be used to communicate with other systems. The testing of Aurora example designs for various configurations are done either by board-to-board testing using standard Bulls eye connectors or SMA connectors. Also external cable loopback tests are performed as part of reset stress testing. The test sequence typically uses Vivado Lab Tools and follows the typical sequence and tests represented in the example design simulation.
To achieve interoperability among different versions of Aurora 64B/66B cores for 7 series FPGA transceivers, a user-level parameter is provided which must be set to achieve proper interoperability between cores as shown in Table: Aurora 64B/66B Interoperability . Table: Aurora 64B/66B Interoperability for 2015.1 and Later Releases shows the interoperability between 7 series FPGAs (2015.1 and later releases) and UltraScale™ FPGAs (2015.1 and later releases) of the Aurora 64B/66B core.
To handle backward compatibility with earlier core versions, three parameters, BACKWARD_COMP_MODE1, BACKWARD_COMP_MODE2 and BACKWARD_COMP_MODE3 are included in the <user_component_name>_core.v module. These parameters allow 2014.1 (7 series FPGAs) core versions to provide the characteristics and functionality of previous versions of the core. These parameters were created to conveniently handle the condition where updates to the previous core versions are not practical. Hence, the overall stability of the linked system (new <-> old) is equivalent to the stability of links achievable between previous core versions (old <-> old) as shown in Table: Aurora 64B/66B Interoperability .
• Default value is 0. This ensures compatibility between 2014.1 (7 series FPGAs) core and 2013.4 (7 series FPGAs) core and between 2014.1 (7 series FPGAs) core and 2013.3 (7 series FPGAs) core.
• Set both these parameters to 1 to make the 2014.1 (7 series FPGAs) core compatible with the 2013.2 (7 series FPGAs) core or with the ISE 14.7 (6 series) core.
• Default value is 0. Set this parameter to 1 (from 2014.3 (7 series FPGAs) core) if the core needs to clear the hot plug counter on reception of any valid BTF. When this parameter is 0, the hot-plug counter is only cleared by reception of CC blocks.