Vivado Design Suite Debug Feature - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

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12.0 English

The Vivado Design Suite debug feature inserts logic analyzer and virtual I/O cores directly into your design. The debug feature also allows you to set trigger conditions to capture application and integrated block port signals in hardware. Captured signals can then be analyzed. This feature in the Vivado IDE is used for logic debugging and validation of a design running in Xilinx.

Note: The init_clk_in clock input is provided as a stable and free running clock to drive the Debug cores and the stability of this clock source is key to ensure the proper debug. You must ensure that this clock is stable before the pma_init input of the IP is de-asserted and that the clock is always stable.