pma_init Staging in the Example Design - 12.0 English

PG074 Aurora 64B/66B LogiCORE IP Product Guide

Document ID
PG074
Release Date
2022-10-19
Version
12.0 English

The top level pma_init input at the example design level is delayed for 128 init_clk cycles ( pma_init_stage ). This signal is pulse-stretched for the duration of a 24-bit counter ( pma_init_assertion ). An aggregate signal from the instantiating logic is provided to the core as the pma_init input. This ensures that the assertion of the pma_init signal to the core results in reset assertion to the entire core.

Inside the <user_component_name>_support_reset_logic.v source file, the debouncer logic (reset_debounce_r) remains in reset state until the gt_reset_in signal ( pma_init_assertion ) is High ensuring an internally generated reset whenever the top level pma_init is asserted. The following figure illustrates this behavior.

Figure 3-7: pma_init Signal Staging

X-Ref Target - Figure 3-7

pg074_pma_init_staging_x14627.jpg

Assertion of the pma_init signal to the core results in hot-plug reset assertion in the channel partner core. The reset sequence after hot-plug reset assertion is shown in the figure below.

Figure 3-8: pma_init Signal Used to Reset Remote System

X-Ref Target - Figure 3-8

pg074_pma_init_to_reset_remote_system_x14628.jpg