Buffering Modules
• AXI4-Stream Clock Converter
Provides clock crossing logic to bridge two clock domains.
• AXI4-Stream Data FIFO
Provides depth of 16 or deeper buffering with support for multiple clocks, ECC, different resource utilization types and optional FIFO Flags.
• AXI4-Stream Register Slice
Creates timing isolation and pipelining master and slave using a two-deep register buffer.
Transform Modules
• AXI4-Stream Combiner
° Aggregates multiple narrow AXI4-Stream transfers in parallel into one master by splicing the TDATA bits together in to create an AXI4-Stream transfer with a wider output.
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LogiCORE IP Facts Table |
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Core Specifics |
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Supported Device Family (1) |
AMD Versal™ Adaptive SoCs, AMD UltraScale+™ Architecture, AMD UltraScale™ Architecture, 7 Series |
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Supported User Interfaces |
AXI4-Stream, AXI4-Lite |
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Resources |
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Provided with Core |
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Design Files |
Verilog RTL |
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Example Design |
Verilog |
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Test Bench |
Verilog |
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Constraints File |
Xilinx Design Constraints (XDC) |
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Simulation Model |
Behavioral Verilog |
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Supported
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N/A |
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Tested Design Flows (2) |
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Design Entry |
AMD Vivado™ Design Suite |
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Simulation |
For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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Synthesis |
Vivado Synthesis |
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Support |
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Release Notes and Known Issues |
Master Answer Record: N/A |
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All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
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Notes: 1. For a complete listing of supported devices, see the Vivado IP Catalog. 2. For the supported versions of the tools, see t he Vivado Design Suite User Guide: Release Notes, Installation, and Licensing. |
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