Features - 3.0 English

AXI4-Stream Infrastructure IP Suite (PG085)

Document ID
Release Date
3.0 English

Buffering Modules

AXI4-Stream Clock Converter

Provides clock crossing logic to bridge two clock domains.

AXI4-Stream Data FIFO

Provides depth of 16 or deeper buffering with support for multiple clocks, ECC, different resource utilization types and optional FIFO Flags.

AXI4-Stream Register Slice

Creates timing isolation and pipelining master and slave using a two-deep register buffer.

Transform Modules

AXI4-Stream Combiner

° Aggregates multiple narrow AXI4-Stream transfers in parallel into one master by splicing the TDATA bits together in to create an AXI4-Stream transfer with a wider output.

LogiCORE IP Facts Table

Core Specifics

Supported Device Family (1)

AMD Versal™ Adaptive SoCs, AMD UltraScale+™ Architecture, AMD UltraScale™ Architecture, 7 Series

Supported User Interfaces

AXI4-Stream, AXI4-Lite


See Table: Latency by Module Type .

Provided with Core

Design Files

Verilog RTL

Example Design


Test Bench


Constraints File

Xilinx Design Constraints (XDC)

Simulation Model

Behavioral Verilog

S/W Driver


Tested Design Flows (2)

Design Entry

AMD Vivado™ Design Suite


For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing.


Vivado Synthesis


Release Notes and Known Issues

Master Answer Record: N/A

All Vivado IP Change Logs

Master Vivado IP Change Logs: 72775

Support web page


1. For a complete listing of supported devices, see the Vivado IP Catalog.

2. For the supported versions of the tools, see t he Vivado Design Suite User Guide: Release Notes, Installation, and Licensing.