When using the AXI4-Stream Register Slice core in either the SLR Crossing, SLR TDM Crossing, or Multi SLR Crossing modes, the constraints must be applied to explicitly floor plan the submodules of the core into adjacent SLRs. This ensures that the SLR crossing occurs between the intended flop-to-flop, unit-fanout, internal wires across all payload and handshake pathways within the core.