The following table shows the revision history for this document.
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Section |
Revision Summary |
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05/24/2023 Version 3.0 |
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Updated the section |
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08/08/2022 Version 3.0 |
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Added UltraScale+ and Versal architecture support. |
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Updated remap string examples in the Extra Settings section. |
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11/17/2021 Version 3.0 |
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Updated Enable URAM Memory Type. |
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12/05/2018 Version 3.0 |
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All chapters |
• Updated for AXI4-Stream Data FIFO core changes: • Added Xilinx Parameterized Macro support. • Updated FIFO depth support, and support for multiple clocks, ECC, various resource utilization types, and optional FIFO flags. • Removed FIFO Generator support. |
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04/04/2018 Version 2.2 |
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Updated AXI4-Stream Switch Arbiter Algorithm, AXI4-Steam Slice parameters, and core constraints. |
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1/29/2017 Version 2.2 |
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Updated AXI4-Stream Register Slice to add user-selectable performance vs. area tradeoff and optional pipelining to cross SLRs in SSI devices. |
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04/05/2017 Version 2.2 |
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Updated for Enable FIFO Count Ports section. |
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04/06/2016 Version 2.2 |
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Updated AXI4-Stream Subset Converter section. |
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04/01/2015 Version 2.2 |
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Updated AXI4-Stream Switch section. |
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10/01/2014 Version 2.2 |
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Updated Table 2-6 . Added Device Migration section. |
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12/18/2013 Version 2.2 |
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All chapters |
Added UltraScale Architecture support. |
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10/02/2013 Version 2.2 |
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Added Example Design and Test Bench chapters. |
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03/20/2013 Version 2.1 |
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Updated Tables 2-3 and 2-5 and revised Debugging appendix. |
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12/18/2012 Version 2.0 |
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Updated for characterization numbers and added Debugging appendix. |
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10/16/2012 Version 1.0 |
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Initial Xilinx release. |
N/A |