The AXI Protocol Checks and descriptions, listed in the following table, correspond to the assertions that are found in the Arm AXI assertions.
| Name of Protocol Check | Bit | Notes | Protocol Support | Description |
|---|---|---|---|---|
| AXI_ERRM_AWADDR_BOUNDARY | 0 | - | AXI4/AXI3 | A write burst cannot cross a 4 KB boundary. |
| AXI_ERRM_AWADDR_WRAP_ALIGN | 1 | - | AXI4/AXI3 | A write transaction with burst type WRAP has an aligned address. |
| AXI_ERRM_AWBURST | 2 | - | AXI4/AXI3 | A value of 2’b11 on AWBURST is not permitted when AWVALID is High. |
| AXI_ERRM_AWLEN_LOCK | 3 | - | AXI4/AXI3 | Exclusive access transactions cannot have a length greater than 16 beats. This check is not implemented. |
| AXI_ERRM_AWCACHE | 4 | - | AXI4/AXI3 | If not cacheable (AWCACHE[1] == 1'b0), AWCACHE = 2'b00. |
| AXI_ERRM_AWLEN_FIXED | 5 | - | AXI4/AXI3 | Transactions of burst type FIXED cannot have a length greater than 16 beats. |
| AXI_ERRM_AWLEN_WRAP | 6 | - | AXI4/AXI3 | A write transaction with burst type WRAP has a length of 2, 4, 8, or 16. |
| AXI_ERRM_AWSIZE | 7 | L 1 | AXI4/AXI3 | The size of a write transfer does not exceed the width of the data interface. |
| AXI_ERRM_AWVALID_RESET | 8 | - | AXI4/AXI3/Lite | AWVALID is Low for the first cycle after ARESETn goes High. |
| AXI_ERRM_AWADDR_STABLE | 9 | - | AXI4/AXI3/Lite | Handshake Checks: AWADDR must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWBURST_STABLE | 10 | - | AXI4/AXI3 | Handshake Checks: AWBURST must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWCACHE_STABLE | 11 | - | AXI4/AXI3 | Handshake Checks: AWCACHE must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWID_STABLE | 12 | - | AXI4/AXI3 | Handshake Checks: AWID must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWLEN_STABLE | 13 | - | AXI4/AXI3 | Handshake Checks: AWLEN must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWLOCK_STABLE | 14 | - | AXI4/AXI3 | Handshake Checks: AWLOCK must remain stable when AWVALID is asserted and AWREADY Low. This check is not implemented. |
| AXI_ERRM_AWPROT_STABLE | 15 | - | AXI4/AXI3/Lite | Handshake Checks: AWPROT must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWSIZE_STABLE | 16 | - | AXI4/AXI3 | Handshake Checks: AWSIZE must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWQOS_STABLE | 17 | - | AXI4/AXI3 | Handshake Checks: AWQOS must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWREGION_STABLE | 18 | - | AXI4 | Handshake Checks: AWREGION must remain stable when ARVALID is asserted and AWREADY Low. |
| AXI_ERRM_AWVALID_STABLE | 19 | - | AXI4/AXI3/Lite | Handshake Checks: Once AWVALID is asserted, it must remain asserted until AWREADY is High. |
| AXI_RECS_AWREADY_MAX_WAIT | 20 | L 1 | AXI4/AXI3/Lite | Recommended that AWREADY is asserted within MAXWAITS cycles of AWVALID being asserted. |
| AXI_ERRM_WDATA_NUM | 21 | L 1 | AXI4/AXI3 |
The number of write data items matches AWLEN for the
corresponding address. This is triggered when any of the
following occurs:
|
| AXI_ERRM_WSTRB | 22 | - | AXI4/AXI3/Lite | Write strobes must only be asserted for the correct byte lanes as determined from the: Start Address, Transfer Size and Beat Number. |
| AXI_ERRM_WVALID_RESET | 23 | - | AXI4/AXI3/Lite | WVALID is LOW for the first cycle after ARESETn goes High. |
| AXI_ERRM_WDATA_STABLE | 24 | - | AXI4/AXI3/Lite | Handshake Checks: WDATA must remain stable when WVALID is asserted and WREADY Low. |
| AXI_ERRM_WLAST_STABLE | 25 | - | AXI4/AXI3 | Handshake Checks: WLAST must remain stable when WVALID is asserted and WREADY Low. |
| AXI_ERRM_WSTRB_STABLE | 26 | - | AXI4/AXI3/Lite | Handshake Checks: WSTRB must remain stable when WVALID is asserted and WREADY Low. |
| AXI_ERRM_WVALID_STABLE | 27 | - | AXI4/AXI3/Lite | Handshake Checks: Once WVALID is asserted, it must remain asserted until WREADY is High. |
| AXI_RECS_WREADY_MAX_WAIT | 28 | L 1 | AXI4/AXI3/Lite | Recommended that WREADY is asserted within MAXWAITS cycles of WVALID being asserted. |
| AXI_ERRS_BRESP_EXOKAY | 30 | - | AXI4/AXI3 | An EXOKAY write response can only be given to an exclusive write access. This check is not implemented. |
| AXI_ERRS_BVALID_RESET | 31 | - | AXI4/AXI3/Lite | BVALID is Low for the first cycle after ARESETn goes High. |
|
AXI_ERRS_BRESP_AW Or AXI_ERRS_BRESP_WLAST |
32 | L 1 | AXI4/AXI3/Lite |
A slave must not take BVALID HIGH until after the write address handshake is complete. Or A slave must not take BVALID HIGH until after the last write data handshake is complete. Note: The IP does not distinguish between
these two causes.
|
| AXI_ERRS_BID_STABLE | 33 | - | AXI4/AXI3 | Handshake Checks: BID must remain stable when BVALID is asserted and BREADY Low. |
| AXI_ERRS_BRESP_STABLE | 34 | - | AXI4/AXI3/Lite | Checks BRESP must remain stable when BVALID is asserted and BREADY Low. |
| AXI_ERRS_BVALID_STABLE | 35 | - | AXI4/AXI3/Lite | Once BVALID is asserted, it must remain asserted until BREADY is High. |
| AXI_RECM_BREADY_MAX_WAIT | 36 | L 1 | AXI4/AXI3/Lite | Recommended that BREADY is asserted within MAXWAITS cycles of BVALID being asserted. |
| AXI_ERRM_ARADDR_BOUNDARY | 37 | - | AXI4/AXI3 | A read burst cannot cross a 4 KB boundary. |
| AXI_ERRM_ARADDR_WRAP_ALIGN | 38 | - | AXI4/AXI3 | A read transaction with a burst type of WRAP must have an aligned address. |
| AXI_ERRM_ARBURST | 39 | - | AXI4/AXI3 | A value of 2'b11 on ARBURST is not permitted when ARVALID is High. |
| AXI_ERRM_ARLEN_LOCK | 40 | - | AXI4/AXI3 | Exclusive access transactions cannot have a length greater than 16 beats. This check is not implemented. |
| AXI_ERRM_ARCACHE | 41 | - | AXI4/AXI3 | When ARVALID is HIGH, if ARCACHE[1] is LOW, then ARCACHE[3:2] must also be Low. |
| AXI_ERRM_ARLEN_FIXED | 42 | - | AXI4/AXI3 | Transactions of burst type FIXED cannot have a length greater than 16 beats. |
| AXI_ERRM_ARLEN_WRAP | 43 | - | AXI4/AXI3 | A read transaction with burst type of WRAP must have a length of 2, 4, 8, or 16. |
| AXI_ERRM_ARSIZE | 44 | L 1 | AXI4/AXI3 | The size of a read transfer must not exceed the width of the data interface. |
| AXI_ERRM_ARVALID_RESET | 45 | - | AXI4/AXI3/Lite | ARVALID is Low for the first cycle after ARESETn goes High. |
| AXI_ERRM_ARADDR_STABLE | 46 | - | AXI4/AXI3/Lite | ARADDR must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARBURST_STABLE | 47 | - | AXI4/AXI3 | ARBURST must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARCACHE_STABLE | 48 | - | AXI4/AXI3 | ARCACHE must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARID_STABLE | 49 | - | AXI4/AXI3 | ARID must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARLEN_STABLE | 50 | - | AXI4/AXI3 | ARLEN must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARLOCK_STABLE | 51 | - | AXI4/AXI3 | ARLOCK must remain stable when ARVALID is asserted and ARREADY Low. This check is not implemented. |
| AXI_ERRM_ARPROT_STABLE | 52 | - | AXI4/AXI3/Lite | ARPROT must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARSIZE_STABLE | 53 | - | AXI4/AXI3 | ARSIZE must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARQOS_STABLE | 54 | - | AXI4/AXI3 | ARQOS must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARREGION_STABLE | 55 | - | AXI4 | ARREGION must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRM_ARVALID_STABLE | 56 | - | AXI4/AXI3/Lite | Once ARVALID is asserted, it must remain asserted until ARREADY is High. |
| AXI_RECS_ARREADY_MAX_WAIT | 57 | L 1 | AXI4/AXI3/Lite | Recommended that ARREADY is asserted within MAXWAITS cycles of ARVALID being asserted. |
| AXI_ERRS_RDATA_NUM | 58 | L 1 | AXI4/AXI3 | The number of read data items must match the corresponding ARLEN. |
| AXI_ERRS_RID | 59 | L 1 | AXI4/AXI3/Lite | The read data must always follow the address that it relates to. If IDs are used, RID must also match ARID of an outstanding address read transaction. This violation can also occur when RVALID is asserted with no preceding AR transfer. |
| AXI_ERRS_RRESP_EXOKAY | 60 | - | AXI4/AXI3 | An EXOKAY write response can only be given to an exclusive read access. This check is not implemented. |
| AXI_ERRS_RVALID_RESET | 61 | - | AXI4/AXI3/Lite | RVALID is Low for the first cycle after ARESETn goes High. |
| AXI_ERRS_RDATA_STABLE | 62 | - | AXI4/AXI3/Lite | RDATA must remain stable when RVALID is asserted and RREADY Low. |
| AXI_ERRS_RID_STABLE | 63 | - | AXI4/AXI3 | RID must remain stable when RVALID is asserted and RREADY Low. |
| AXI_ERRS_RLAST_STABLE | 64 | - | AXI4/AXI3 | RLAST must remain stable when RVALID is asserted and RREADY Low. |
| AXI_ERRS_RRESP_STABLE | 65 | - | AXI4/AXI3/Lite | RRESP must remain stable when RVALID is asserted and RREADY Low. |
| AXI_ERRS_RVALID_STABLE | 66 | - | AXI4/AXI3/Lite | Once RVALID is asserted, it must remain asserted until RREADY is High. |
| AXI_RECM_RREADY_MAX_WAIT | 67 | L 1 | AXI4/AXI3/Lite | Recommended that RREADY is asserted within MAXWAITS cycles of RVALID being asserted. |
| AXI_ERRM_EXCL_ALIGN | 68 | - | AXI4/AXI3 | The address of an exclusive access is aligned to the total number of bytes in the transaction. This check is not implemented. |
| AXI_ERRM_EXCL_LEN | 69 | - | AXI4/AXI3 | The number of bytes to be transferred in an exclusive access burst is a power of 2, that is, 1, 2, 4, 8, 16, 32, 64, or 128 bytes. This check is not implemented. |
| AXI_RECM_EXCL_MATCH | 70 | - | AXI4/AXI3 | Recommended that the address, size, and length of an exclusive write with a given ID is the same as the address, size, and length of the preceding exclusive read with the same ID. This check is not implemented. |
| AXI_ERRM_EXCL_MAX | 71 | - | AXI4/AXI3 | 128 is the maximum number of bytes that can be transferred in an exclusive burst. This check is not implemented. |
| AXI_RECM_EXCL_PAIR | 72 | - | AXI4/AXI3 | Recommended that every exclusive write has an earlier outstanding exclusive read with the same ID. This check is not implemented. |
| AXI_ERRM_AWUSER_STABLE | 73 | - | AXI4/AXI3 | AWUSER must remain stable when AWVALID is asserted and AWREADY Low. |
| AXI_ERRM_WUSER_STABLE | 74 | - | AXI4/AXI3 | WUSER must remain stable when WVALID is asserted and WREADY Low. |
| AXI_ERRS_BUSER_STABLE | 75 | - | AXI4/AXI3 | BUSER must remain stable when BVALID is asserted and BREADY Low. |
| AXI_ERRM_ARUSER_STABLE | 76 | - | AXI4/AXI3 | ARUSER must remain stable when ARVALID is asserted and ARREADY Low. |
| AXI_ERRS_RUSER_STABLE | 77 | - | AXI4/AXI3 | RUSER must remain stable when RVALID is asserted and RREADY Low. |
| AXI_AUXM_RCAM_OVERFLOW | 78 | L 1 | AXI4/AXI3/Lite |
Read CAM overflow. The number of outstanding read transactions exceeds the capacity of the storage implemented in the Protocol Checker core. This does not indicate any failure of the system being monitored, but it might render any subsequent monitoring results invalid. To resolve this, increase MAX_RD_BURSTS parameter. |
| AXI_AUXM_RCAM_UNDERFLOW | 79 | - | AXI4/AXI3/Lite | Read CAM underflow. |
| AXI_AUXM_WCAM_OVERFLOW | 80 | L 1 | AXI4/AXI3/Lite | Write CAM overflow. The number of outstanding write transactions exceeds the capacity of the storage implemented in the Protocol Checker core. This does not indicate any failure of the system being monitored, but it might render any subsequent monitoring results invalid. To resolve this, increase MAX_WR_BURSTS parameter. |
| AXI_AUXM_WCAM_UNDERFLOW | 81 | - | AXI4/AXI3/Lite | Write CAM underflow. |
| AXI_AUXM_EXCL_OVERFLOW | 82 | - | AXI4/AXI3 | Exclusive access monitor overflow. |
| AXI4LITE_ERRS_BRESP_EXOKAY | 83 | - | Lite | A slave must not give an EXOKAY response on an AXI4-Lite interface. |
| AXI4LITE_ERRS_RRESP_EXOKAY | 84 | - | Lite | A slave must not give an EXOKAY response on an AXI4-Lite interface. |
| AXI4LITE_AUXM_DATA_WIDTH | 85 | - | Lite | DATA_WIDTH parameter is 32 or 64. |
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