Control Register Slave Port Descriptions - 2.0 English

AXI Protocol Checker LogiCORE IP Product Guide (PG101)
Document ID
PG101
Release Date
2023-06-21
Version
2.0 English

The following table lists the interface signals for the AXI4-Lite control register slave interface, when enabled. The control register slave interface is read-only.

Table 1. Control Register Slave Port Descriptions
SignalName Direction Default Width Description
s_axi_araddr Input Required 10 Read Address
s_axi_arvalid Input Required 1 Read Address Channel Valid
s_axi_arready Output Required 1 Read Address Channel Ready
s_axi_rdata Output 32 Read Data
s_axi_rresp Output 2 Read Response code (always 0)
s_axi_rvalid Output Required 1 Read Data Channel Valid
s_axi_rready Input Required 1 Read Data Channel Ready