If there are bits asserted in the pc_status vector and the source/reason
of the violation using AXI Protocol Checks and Descriptions is not clear,
move the AXI Protocol Checker “upstream” toward the AXI Master generating the
transactions.
If there are bits asserted in the pc_status vector and the source/reason
of the violation using AXI Protocol Checks and Descriptions is not clear,
move the AXI Protocol Checker “upstream” toward the AXI Master generating the
transactions.