Monitor Port Descriptions for AXI4 Protocol - 2.0 English

AXI Protocol Checker LogiCORE IP Product Guide (PG101)

Document ID
PG101
Release Date
2023-06-21
Version
2.0 English

The following table lists the interface signals for the AXI Protocol Checker monitor interface when it is configured to check an AXI4 Interface.

Table 1. AXI4 Protocol Port Descriptions
Signal Name Direction Default Width Description
pc_axi_awid Input 0 ID_WIDTH Write Address Channel Transaction ID
pc_axi_awaddr Input Required ADDR_WIDTH Write Address Channel Transaction Address (12-64)
pc_axi_awlen Input 0 8 Write Address Channel Transaction Burst Length (0-255)
pc_axi_awsize Input Required 3 Write Address Channel Transfer Size Code (0-7)
pc_axi_awburst Input Required 2 Write Address Channel Burst Type Code (0-2)
pc_axi_awlock Input 0b0 1 Write Address Channel Atomic Access Type (0-1)
pc_axi_awcache Input 0b0000 4 Write Address Channel Cache Characteristics
pc_axi_awprot Input 0b000 3 Write Address Channel Protection Characteristics
pc_axi_awqos Input 0b0000 4 Write Address Channel Quality of Service
pc_axi_awregion Input 0b0000 4 Write Address Channel Region Index
pc_axi_awuser Input AWUSER_WIDTH Write Address Channel User-Defined Signals
pc_axi_awvalid Input Required 1 Write Address Channel Valid
pc_axi_awready Input Required 1 Write Address Channel Ready
pc_axi_arid Input 0 ID_WIDTH Read Address Channel Transaction ID
pc_axi_araddr Input Required ADDR_WIDTH Read Address Channel Transaction Address (12-64)
pc_axi_arlen Input 0 8 Read Address Channel Transaction Burst Length (0-255)
pc_axi_arsize Input Required 3 Read Address Channel Transfer Size Code (0-7)
pc_axi_arburst Input Required 2 Read Address Channel Burst Type Code (0-2)
pc_axi_arlock Input 0b0 1 Read Address Channel Atomic Access Type (0-1)
pc_axi_arcache Input 0b0000 4 Read Address Channel Cache Characteristics
pc_axi_arprot Input 0b000 3 Read Address Channel Protection Characteristics
pc_axi_arqos Input 0b0000 4 Read Address Channel Quality of Service
pc_axi_arregion Input 0b0000 4 Read Address Channel Region Index
pc_axi_aruser Input ARUSER_WIDTH Read Address Channel User-Defined Signals
pc_axi_arvalid Input Required 1 Read Address Channel Valid
pc_axi_arready Input Required 1 Read Address Channel Ready
pc_axi_wlast Input 0b1 1 Write Data Channel Last Data Beat
pc_axi_wdata Input DATA_WIDTH Write Data Channel Data
pc_axi_wstrb Input All Ones DATA_WIDTH/8 Write Data Channel Byte Strobes
pc_axi_wuser Input WUSER_WIDTH Write Data Channel User-Defined Signal
pc_axi_wvalid Input Required 1 Write Data Channel Valid
pc_axi_wready Input Required 1 Write Data Channel Ready
pc_axi_rid Input ID_WIDTH Read Data Channel Transaction ID
pc_axi_rlast Input 1 1 Read Data Channel Last Data Beat
pc_axi_rdata Input DATA_WIDTH Read Data Channel Data
pc_axi_rresp Input 0b00 2 Read Data Channel Response code (0-3)
pc_axi_ruser Input RUSER_WIDTH Read Data Channel User-Defined Signal
pc_axi_rvalid Input Required 1 Read Data Channel Valid
pc_axi_rready Input Required 1 Read Data Channel Ready
pc_axi_bid Input ID_WIDTH Write Response Channel Transaction ID
pc_axi_bresp Input 0b00 2 Write Response Channel Response Code (0-3)
pc_axi_buser Input BUSER_WIDTH Write Response Channel User-Defined Signal
pc_axi_bvalid Input Required 1 Write Response Channel Valid
pc_axi_bready Input Required 1 Write Response Channel Ready