Parameter Checker Options - 2.0 English

AXI Protocol Checker LogiCORE IP Product Guide (PG101)
Document ID
PG101
Release Date
2023-06-21
Version
2.0 English
Maximum outstanding READ transactions
Specifies the depth of the FIFOs for storing the outstanding Read transactions. The value should be equal to or greater than the number of outstanding Read transactions expected for that connection.
Maximum outstanding WRITE transactions
Specifies the depth of the FIFOs for storing the outstanding Write transactions. The value should be equal to or greater than the number of outstanding Write transactions expected for that connection.
Maximum number of idle cycles for AWREADY monitoring
This parameter specifies the maximum number of cycles between the assertion of awvalid to the assertion of awready before an ERROR is generated. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for ARREADY monitoring
This parameter specifies the maximum number of cycles between the assertion of arvalid to the assertion of arready before an ERROR is generated. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for WREADY monitoring
This parameter specifies the maximum number of cycles between the assertion of wvalid to the assertion of wready before an ERROR is generated. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for RREADY monitoring
This parameter specifies the maximum number of cycles between the assertion of rvalid to the assertion of rready before an ERROR is generated. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for BREADY monitoring
This parameter specifies the maximum number of cycles between the assertion of bvalid to the assertion of bready before an ERROR is generated. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for RVALID monitoring after AR command
This parameter specifies the maximum number of idle cycles for RVALID monitoring after AR command transfer. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for WVALID monitoring after AW command
This parameter specifies the maximum number of idle cycles for WVALID monitoring after AW command transfer. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for AWVALID monitoring after a W-channel burst completes
This parameter specifies the maximum number of idle cycles for AWVALID monitoring after a WLAST transfer. When the value is set to 0, this check is disabled.
Maximum number of idle cycles for BVALID monitoring after a write burst completes
This parameter specifies the maximum number of idle cycles for BVALID monitoring after a write burst completes. When the value is set to 0, this check is disabled.
Simulation Log Messaging Level
When a violation is triggered, this parameter allows the core to indicate to the simulation log file different error levels or to disable all messaging entirely. It is also possible to use this parameter to stop or finish the simulation upon a protocol violation occurrence.
Xilinx Connection Checking of Supports Narrow Bursts
If set to no, this parameter specifies that the protocol checker should trap narrow burst violations on the connection. This attribute is not available for AXI4-Lite interfaces.
Note: This value is automatically set when using IP integrator.
Xilinx Maximum Connection Burst Length
The protocol checker should trap transactions lengths which exceed the value indicated by this parameter. The default value varies by protocol and is not available for AXI4-Lite interfaces.
Note: This value is automatically set when using IP integrator.
Enable system reset interface
Enables the system_resetn port. When disabled, the port is tied High.
Only check for bus-hang conditions between protocol-compliant IP
Configures core in Lightweight mode. Only useful when implementing in hardware. Reduces implementation resources by disabling checks that are not likely to cause the connected AXI network to hang.
Enable S_AXI status interface
Enables the AXI4-Lite control register slave interface.
Enable Mark_Debug
When enabled, the set mark_debug attribute is set to True on the pc_status output bus upon synthesis. Disabling this attribute sets the mark_debug attribute to false.
Detect RD/WR SLVERR and DECERR
When set to Yes, this checker detects SLVERR, DECERR response on Read, Write channels. Detection is off when the parameter checker is set to No.