The AXI Protocol Checker monitors the connection
for AXI4, AXI3, and
AXI4-Lite protocol violations. The AXI Protocol Checker is designed around the
Arm®
System Verilog assertions that have been converted into synthesizable HDL. When a protocol
violation occurs, the AXI Protocol Checker asserts the corresponding bit on the pc_status output vector. The output vector bit mapping can be found
in AXI Protocol Checks and Descriptions and AMD-Specific Configuration Checks and Descriptions. The value of the
status vector can also be read via the optional AXI4-Lite
control register slave interface.
Bits of the pc_status vector are
synchronously set when a protocol violation occurs. Multiple bits can be triggered on the same
or different cycles. When the bit within the pc_status vector
has been set, it remains asserted until the connection has been reset with aresetn, or the core has been reset with system_resetn. The pc_asserted output signal is
also asserted while any bit of the pc_status vector is
asserted.