System Reset and AXI Reset - 2.0 English

AXI Protocol Checker LogiCORE IP Product Guide (PG101)

Document ID
PG101
Release Date
2023-06-21
Version
2.0 English

At a minimum, the AXI Protocol Checker requires the aresetn signal. system_resetn can be configured to clear the pc_status vector without resetting the AXI4 interface. Both reset inputs are synchronous to aclk. The assertion of either reset clears the pc_status vector and the pc_asserted output.

Note: AMD recommends asserting aresetn for a minimum of 16 clock cycles.

If system_resetn is enabled, the Protocol Checker can check the AXI4 specification which defines the state of the interface following the de-assertion of aresetn . Protocol violation notifications related to the required behavior of interfaces with respect to aresetn are cleared using system_resetn.

When a system reset is not available, system_resetn should be disabled. When this is done, the following checks are not possible:

  • AXI_ERRM_AWVALID_RESET
  • AXI_ERRM_ARVALID_RESET
  • AXI_ERRM_WVALID_RESET
  • AXI_ERRM_RVALID_RESET
  • AXI_ERRM_BVALID_RESET
  • XILINX_AWREADY_RESET
  • XILINX_WREADY_RESET
  • XILINX_BREADY_RESET
  • XILINX_ARREADY_RESET
  • XILINX_RREADY_RESET