The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).
Vivado IDE Parameter/Value | User Parameter/Value | Default Value |
---|---|---|
Connection Protocol | PROTOCOL | AXI4 |
READ_WRITE Mode | READ_WRITE_MODE | READ_WRITE |
Address Width | ADDR_WIDTH | 32 |
Data Width | DATA_WIDTH | 32 |
ID Width | ID_WIDTH | 0 |
AWUSER Width | AWUSER_WIDTH | 0 |
ARUSER Width | ARUSER_WIDTH | 0 |
WUSER Width | WUSER_WIDTH | 0 |
RUSER Width | RUSER_WIDTH | 0 |
BUSER Width | BUSER_WIDTH | 0 |
Maximum Outstanding Read Transactions | MAX_RD_BURSTS | 8 |
Maximum Outstanding Write Transactions | MAX_WR_BURSTS | 8 |
Maximum Number of Idle Cycles for AWREADY Monitoring 1 | MAX_AW_WAITS | 0 (disabled) |
Maximum Number of Idle Cycles for ARREADY Monitoring 1 | MAX_AR_WAITS | 0 (disabled) |
Maximum Number of Idle Cycles for WREADY Monitoring 1 | MAX_W_WAITS | 0 (disabled) |
Maximum Number of Idle Cycles for RREADY Monitoring 1 | MAX_R_WAITS | 0 (disabled) |
Maximum Number of Idle Cycles for BREADY Monitoring 1 | MAX_B_WAITS | 0 (disabled) |
Maximum number of idle cycles for RVALID monitoring after AR command 1 | MAX_CONTINUOUS_RTRANSFERS_WAITS | 0 (disabled) |
Maximum number of idle cycles for WVALID monitoring after AW command 1 | MAX_CONTINUOUS_WTRANSFERS_WAITS | 0 (disabled) |
Maximum number of idle cycles for AWVALID monitoring after a W-channel burst completes 1 | MAX_WLAST_TO_AWVALID_WAITS | 0 (disabled) |
Maximum number of idle cycles for BVALID monitoring after a write burst completes 1 | MAX_WRITE_TO_BVALID_WAITS | 0 (disabled) |
Simulation Log Messaging Level
|
MESSAGE_LEVEL
|
2 (Error) |
Xilinx Connection Checking of Supports Narrow Burst
|
SUPPORTS_NARROW_BURST
|
1 (Yes) |
Xilinx Maximum Connection Burst Length | MAX_BURST_LENGTH | 256 |
Enable System Reset Interface
|
HAS_SYSTEM_RESET
|
0 (No) |
Only check for bus-hang conditions between protocol-compliant
IP
|
LIGHT_WEIGHT
|
0 (No) |
Enable S_AXI status interface
|
ENABLE_CONTROL
|
0 (No) |
Enable Mark_Debug on pc_status
|
ENABLE_Mark_Debug
|
1 (Yes) |
Detect RD/WR SLVERR and DECERR
|
CHK_ERR_RESP
|
0 (No) |
|