The AXI4 Memory mapped transfers are packed onto the AXI4-Stream TDATA signal. This section describes how the AXI4 transactions are mapped.
The AXI4 Memory Mapped to AXI4-Stream TDATA packing is shown in This Figure .
The AXI4 Memory Mapped signals are packed onto the LSB of the TDATA signals. With an address of 32 bits and a 4-bit ID, 9 bytes of TDATA are needed to map the address channels. If the address or ID are reduced by 1 bit, then the transfer can fit into 8 bytes of TDATA . Adding USER bits may cause a spillover into nine or more bytes, which may cause degraded performance.
The write data channel requires 5 bytes of TDATA if a WDATA width of 4 bytes is configured. Assuming no user signals, the number of TDATA bytes required for each of the WDATA widths in the write channel can be calculated as:
where W x is the width in bytes of signal x .
The read address, write address, and write data channels are multiplexed onto one outgoing Stream and are zero padded at the end to extend the packing width to be an integer multiple of the specified TDATA width. A downsizer will then be used to appropriately split the transactions if necessary.
The write response channel always requires 1 byte of TDATA or more if BID exceeds 6 bits.
The read data channel always requires a minimum of the number of RDATA bytes + 1.
The write response and the read data channels are expanded from one incoming stream. An upsizer is used to merge the transactions back to one transfer if necessary.