The AXI4-Stream TID signal is utilized to distinguish the individual AXI4 memory mapped channels. The TID bits are necessary at the receiving end of each of the AXI4-Stream channels to demultiplex back to the memory mapped interface. The TID signals can be monitored along with the TDATA signal to verify proper transport of the encapsulated data. The TID to the memory mapped AXI4 channel mappings are described the following table.
|
AXI4 Channel |
TID Value |
Description |
|---|---|---|
|
AW |
0b001 |
Write Address |
|
W |
0b100 |
Write Data |
|
B |
0b000 |
Write Response |
|
AR |
0b010 |
Read Address |
|
R |
0b011 |
Read Data |