AXI4-Lite Interface - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

The AXI4-Lite interface allows you to dynamically control parameters within the core. Core configuration can be accomplished using an AXI4-Lite master state machine, or an embedded Arm® or soft system processor such as MicroBlaze™.

The TPG core can be controlled through the AXI4-Lite interface by using functions provided by the driver in the Vitis™ software platform. Another method is performing read and write transactions to the TPG register space but should only be used when the first method is not available.

Table 2-3: AXI4-Lite Interface Signals

Signal Name

Direction

Width

Description

s_axi_CTRL_awvalid

In

1

AXI4-Lite Write Address Channel Write Address Valid.

s_axi_CTRL_awready

Out

1

AXI4-Lite Write Address Channel Write Address Ready. Indicates DMA ready to accept the write address.

s_axi_CTRL_awaddr

In

8

AXI4-Lite Write Address Bus

s_axi_CTRL_wvalid

In

1

AXI4-Lite Write Data Channel Write Data Valid.

s_axi_CTRL_wready

Out

1

AXI4-Lite Write Data Channel Write Data Ready. Indicates DMA is ready to accept the write data.

s_axi_CTRL_wdata

In

32

AXI4-Lite Write Data Bus

s_axi_CTRL_bresp

Out

2

AXI4-Lite Write Response Channel. Indicates results of the write transfer.

s_axi_CTRL_bvalid

Out

1

AXI4-Lite Write Response Channel Response Valid. Indicates response is valid.

s_axi_CTRL_bready

In

1

AXI4-Lite Write Response Channel Ready. Indicates target is ready to receive response.

s_axi_CTRL_arvalid

In

1

AXI4-Lite Read Address Channel Read Address Valid

s_axi_CTRL_arready

Out

1

Ready. Indicates DMA is ready to accept the read address.

s_axi_CTRL_araddr

In

8

AXI4-Lite Read Address Bus

s_axi_CTRL_rvalid

Out

1

AXI4-Lite Read Data Channel Read Data Valid

s_axi_CTRL_rready

In

1

AXI4-Lite Read Data Channel Read Data Ready. Indicates target is ready to accept the read data.

s_axi_CTRL_rdata

Out

32

AXI4-Lite Read Data Bus

s_axi_CTRL_rresp

Out

2

AXI4-Lite Read Response Channel Response. Indicates results of the read transfer.

s_axi_CTRL_wstrb

In

4

AXI4-Lite Write Strobe. Shows which bytes of the data bus are valid and should be read by the Slave.