Background Pattern ID (0x0020) Register - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

The Background Pattern ID register controls the majority of the pattern manipulations that the TPG core produces.

This register controls which patterns are generated on the output of the core based on the following values:

0x00 - Pass the video input straight through the video output

0x1 - Horizontal Ramp which increases each component (RGB or Y) horizontally by 1

0x2 - Vertical Ramp which increases each component (RGB or Y) vertically by 1

0x3 - Temporal Ramp which increases every pixel by a value set in the motion speed register for every frame.

0x4 - Solid red output

0x5 - Solid green output

0x6 - Solid blue output

0x7 - Solid black output

0x8 - Solid white output

0x9 - Color bars

0xA - Zone Plate output produces a ROM based sinusoidal pattern. This option has dependencies on the motion speed, zplate horizontal starting point, zplate horizontal delta, zplate vertical starting point, and zplate vertical delta registers.

0xB - Tartan Color Bars

0xC - Draws a cross hatch pattern

0xD - Color sweep pattern

0xE - A combined vertical and horizontal ramp

0xF - Black and white checker board

0x10 - Pseudorandom pattern

0x11 - DisplayPort color ramp

0x12 - DisplayPort black and white vertical lines

0x13 - DisplayPort color square

In addition to setting the background pattern ID register with the correct value, the relative pattern category must be enabled when customizing IP to generate a desired pattern during runtime. If some pattern categories are disabled, the TPG generates a pure black screen when the background pattern ID register is configured with a pattern in a disabled category. For more information about the background pattern categorization, refer to Design Flow Steps .