Detailed Example Design - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

This chapter provides two example systems that include the Video Test Pattern Generator core. One is simulation example design and the other one is synthesizable example design. Important system-level aspects when designing with the Video Test Pattern Generator are highlighted in example designs, including:

Video test pattern generator usage in AXI4-Stream Slave enable and disable mode.

Typical usage of video test pattern generator in conjunction with other cores and AXI master.

Configuration of video test pattern generation registers on the fly.

Note: The example project is only available on Xilinx ® KC705 evaluation board.

Table 5-1: Example Design Support

Development Board

Additional Hardware

Processor

Topology

KC705

N/A

MicroBlaze

Generator or Passthrough

ZCU102

N/A

psu_cortexa53_0

Generator or Passthrough

ZCU104

N/A

psu_cortexa53_0

Generator or Passthrough

ZCU106

N/A

psu_cortexa53_0

Generator or Passthrough

VCK190

N/A

CIPS

Generator or Passthrough

To open the example project, perform following:

1. Select the Video Test Pattern Generator IP from IP Catalog.

2. Double-click on the selected IP or right-click the IP and select Customize IP from the menu.

3. Configure the build-time parameters in the Customize IP window and click OK . The Vivado ® IDE generates an example design matching the build-time configuration.

4. In the Generate Output Products window, select Generate or Skip . If Generate is selected, the IP’s output products are generated after a brief moment.

5. Right-click TPG in Sources panel and select Open IP Example Design from the menu.

6. In the Open IP Example Design window, select example project directory and click OK . The Vivado software then runs automation to generate example design in selected directory.

The generated project contains two example designs. This Figure shows the Source panel of the example project. Synthesizable example block design, along with top-level file, resides in Design Sources catalog. Corresponding constraint file is also provided for the synthesizable example design. Simulation example design files (including block design file, SystemVerilog test bench and another task file) are under Simulation Sources.

Figure 5-1: Example Project Source Panel

X-Ref Target - Figure 5-1

exampleGUI.png