Maximum Frequencies - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

There are no IP specific restrictions on the maximum achievable clock frequency. The restriction is dependent on if the design can meet timing or not. Meeting timing is dependent on the clock frequency selected, and is impacted by resource utilization, tool options, additional logic in the device and the version of tool used. For more information, see Xilinx® timing closure documentation as well as the fabric data-sheets below. The frequency ranges specified in these documents must be adhered to for proper transceiver and core operation.

Kintex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS892) [Ref 9]

Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref 10]

Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182) [Ref 11]

Virtex-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS183) [Ref 12]

Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181) [Ref 13]

Zynq-7000 SoC (Z-7007S, Z-7012S, Z-7014S, Z-7010, Z-7015, and Z-7020) Data Sheet: DC and AC Switching Characteristics (DS187) [Ref 14]

Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100) Data Sheet: DC and AC Switching Characteristics (DS191) [Ref 15]

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref 16]

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923) [Ref 17]

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 18]

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) [Ref 19]

Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957)
[Ref 20]