Port Descriptions - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

The Video Test Pattern Generator core uses industry standard control and data interfaces to connect to other system components. The following sections describe the various interfaces available with the core. This Figure illustrates an I/O diagram of the TPG core. Some signals are optional and not present for all configurations of the core. The AXI4-Lite interface is always available while the AXI4-Stream slave interface is optional.

Figure 2-1: TPG Core Top-Level Signaling Interface

X-Ref Target - Figure 2-1

X15054-tpg-core-diagram.jpg