Register Space - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

The core has 26 core-specific registers which allow you to dynamically control the operation of the core. All registers have initial value of 0. Table: Register Names and Descriptions describes the register names.

Table 2-4: Register Names and Descriptions

Address (hex) BASEADDR +

Register Name

Access Type

Register Description

0x0000

Control

R/W

Bit 0: ap_start (R/W/COH) (1)

Bit 1: ap_done (R/COR) (1)

Bit 2: ap_idle (R)

Bit 3: ap_ready (R)

Bit 7: auto_restart (R/W)

Others: reserved

0x0004

Global Interrupt Enable

R/W

Bit 0: Global Interrupt Enable

Others: reserved

This register is not used but reserved for future use.

0x0008

IP Interrupt Enable Register

R/W

Bit 0: Channel 0 (ap_done)

Bit 1: Channel 1 (ap_ready)

Others: reserved

This register is not used but reserved for future use.

0x000C

IP Interrupt Status Register

R

Bit 0: Channel 0 (ap_done)

Bit 1: Channel 1 (ap_ready)

Others: reserved

This register is not used but reserved for future use.

0x0010

Active height

R/W

Number of Active Lines per Frame

0x0018

Active width

R/W

Number of Active Pixels per Scanline

0x0020

Background pattern ID

R/W

Background pattern selection.

0x0028

Overlay ID

R/W

Foreground pattern selection.

0x0030

Mask ID

R/W

Color mask selection.

0x0038

Motion speed

R/W

How quickly the temporal features of the supported test pattern change from frame to frame

0x0040

Color format

R/W

Specify video color format

0x0048

Cross hair horizontal

R/W

Horizontal cross hair location

0x0050

Cross hair vertical

R/W

Vertical cross hair location

0x0058

zplate horizontal starting point

R/W

Set a starting point based sinusoidal values for the horizontal component

0x0060

zplate horizontal delta

R/W

Manipulates how quickly the horizontal component changes

0x0068

zplate vertical starting point

R/W

Set a starting point based sinusoidal values for the vertical component

0x0070

zplate vertical delta

R/W

Manipulates how quickly the vertical component changes

0x0078

Box size

R/W

Size of the box in pixel x pixel

Bit [7:0]: Width of the box

Bit [15:8]: Height of the box

Since it is a NxN box, width and height are same.

0x0080

Box Color R and Y

R/W

Red, Y component value of the box

0x0088

Box Color G and U

R/W

Green, U component value of the box

0x0090

Box Color B and V

R/W

Blue, V component value of the box

0x0098

Enable input

R/W

Indicate whether to make use of video stream entering slave AXI4-Stream video interface.

Takes effect only when AXI4-Stream slave interface is enabled.

0x00A0

Pass through left boundary

R/W

Left boundary (inclusively) of pass through window of video stream entering slave AXI4-Stream video interface.

Takes effect only when AXI4-Stream slave interface is enabled.

0x00A8

Pass through right boundary

R/W

Right boundary (exclusively) of pass through window of video stream entering slave AXI4-Stream video interface.

Takes effect only when AXI4-Stream slave interface is enabled.

0x00B0

Pass through upper boundary

R/W

Upper boundary (inclusively) of pass through window of video stream entering slave AXI4-Stream video interface.

Takes effect only when AXI4-Stream slave interface is enabled.

0x00B8

Pass through lower boundary

R/W

Lower boundary (exclusively) of pass through window of video stream entering slave AXI4-Stream video interface.

Takes effect only when AXI4-Stream slave interface is enabled.

0x00C0

Display port dynamic change

R/W

Dynamic range of DisplayPort color square in RGB.

Takes effect only when DisplayPort color square pattern is selected.

0x00C8

Display port YUV coefficients

R/W

Co-efficients of DisplayPort color square in YUV.

Takes effect only when DisplayPort color square pattern is selected.

0x00D0

Field ID

R/W

Used to configure the Field ID port of this block. Takes effect only for interlaced video content. Default value is 0.

Bit 0: Progressive or Interlaced bit

0 - Progressive

1 - Interlaced

Bit 1: Polarity bit

0 - Low during Field 0 and High during Field 1

1 - High during Field 0 and Low during Field 1

Bit 2: Passthrough enable bit

0 - Generator mode

1 - Passthrough mode

Bit [31:3]: Reserved.

0x00D8

Back Motion Enable

R/W

Enables or disables the horizontal motion of the color bars pattern.

0x0 - Disable motion

0x1 - Enable motion

Notes:

1. COH = Clear on Handshake, COR = Clear on Read

2. Control Register (0x0000), Global Interrupt Enable Register (0x0004), IP Interrupt Enable Register (0x0008), and IP Interrupt Status Register (0x000C) are explained in section S_AXILITE Control Register Map of Vitis High-Level Synthesis User Guide (UG1399) [Ref 21] . These registers definitions may have some additional bits; however, in the current IP, we are accessing only bits mentioned in Table: Register Names and Descriptions . Therefore, only these bits need to be considered while accessing the Control Register, Global Interrupt Enable Register, IP Interrupt Enable Register, and IP Interrupt Status Register.