System Considerations - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

The Video Test Pattern Generator IP core must be configured for the actual input image frame-size to operate properly. To gather the frame size information from the image video stream, it can be connected to the Video In to AXI4-Stream input and the Video Timing Controller. The timing detector logic in the Video Timing Controller gathers the video timing signals. The AXI4-Lite control interface on the Video Timing Controller allows the system processor to read out the measured frame dimensions, and program all downstream cores, such as the TPG, with the appropriate image dimensions.

When the Video Test Pattern Generator switches from Pass Through mode to generating a test pattern, the TPG uses an internal timing mechanism to produce Video over AXI4-Stream timing information.