Video Data - 8.2 English

PG103 Video Test Pattern Generator

Document ID
PG103
Release Date
2022-05-11
Version
8.2 English

The AXI4-Stream interface specification restricts TDATA widths to integer multiples of 8 bits. Therefore, any bit data must be padded with zeros on the MSB to form a N*8 bit wide vector before connecting to s_axis_video_tdata . Padding does not affect the size of the core.

Similarly, data on the TPG output m_axis_video_tdata is packed and padded to multiples of 8 bits as necessary. Zero padding the most significant bits is only necessary for 10 and 12 bit wide data. This Figure through This Figure explain the pixel mapping of AXI4-Stream interface with 2 pixels per clock and 10 bits per component configuration for all supporting color formats. Zero padding (bits [63:60]) is not shown in the figures. Given that TPG requires hardware configuration for 3 component video, the AXI4-Stream Subset Converter is needed to hook up with other IPs of 2 component video interface in YUV 4:2:2 and YUV 4:2:0 color format. Refer to Upgrading and AXI4-Stream Video IP and System Design Guide (UG934) [Ref 4] for more information.

Figure 2-2: Dual Pixels per Clock, 10 bits per Component Mapping for RGB

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Figure 2-3: Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:4:4

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Figure 2-4: Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:2:2

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Figure 2-5: Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:2:0 Even Line

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Figure 2-6: Dual Pixels per Clock, 10 bits per Component Mapping for YUV 4:2:0 Odd Line

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