Demonstration Test Bench in Detail - 9.1 English

PG109 Fast Fourier Transform LogiCORE IP Product Guide

Document ID
PG109
Release Date
2022-05-04
Version
9.1 English

The demonstration test bench performs the following tasks:

Instantiates the core

Generates an input data frame consisting of one or the sum of two complex sinusoids

Generates a clock signal

Drives the core input signals to demonstrate core features

Checks that the core output signals obey AXI protocol rules (data values are not checked to keep the test bench simple)

Provides signals showing the separate fields of AXI TDATA and TUSER signals

The demonstration test bench drives the core input signals to demonstrate the features and modes of operation of the core. This includes performing an FFT on a pre-generated input data frame. The input data frame consists of a complex sinusoid with a frequency of 2.6 times the frame size. The FFT of this input frame is a peak centred between output samples 2 and 3. For FFTs with a maximum point size of 64 or greater, the input data is modified by adding a second complex sinusoid with a frequency of 23.2 times the frame size and a quarter of the magnitude of the first sinusoid. This modifies the FFT by adding a smaller peak centred between output samples 23 and 24. The test bench captures this output frame and uses it as the input frame for an inverse transform. The output of this inverse transform is therefore the same as the original input frame (modified by the scaling and finite precision effects of the FFT core).

The operations performed by the demonstration test bench are appropriate for the configuration of the generated core, and are a subset of the following operations:

Frame 1: drive a frame of pre-generated input data

Frame 2: configure an inverse transform; drive the output of frame 1 as a frame of input data

Configure frame 3: a forward transform while the previous transform is running

Frame 3: drive the output of frame 2 as a frame of input data; deassert AXI TVALID (and TREADY if present) signals occasionally to demonstrate AXI handshaking

If ARESETn present: start another frame but reset the core before it completes

Frames 4-7: run these back-to-back, as quickly as possible:

° Queue up configurations for a forward transform (frame 4) followed by a reverse transform (frame 5), both with a smaller point size (if point size is configurable) and a short cyclic prefix (if available)

° Frame 4: drive a frame of pre-generated input data

° Frame 5: drive the output of frame 1 as a frame of input data; simultaneously configure frame 6: a forward transform with maximum point size, a longer cyclic prefix (if available) and a zero scaling schedule (if fixed scaling is used)

° Frame 6: drive a frame of pre-generated input data; simultaneously configure frame 7: an inverse transform with maximum point size, no cyclic prefix and default scaling schedule (if fixed scaling is used)

° Frame 7: drive the output of frame 1 as a frame of input data

Wait until all frames are complete