• Data Format : Select whether the input and output data samples are in Fixed-Point format, or in IEEE-754 single precision (32-bit) Floating-Point format. Floating-Point format is not available when the core is in a multichannel configuration.
• Precision Options : Input data and phase factors can be independently configured to widths from 8 to 34 bits, inclusive. When the Data Format is Floating-Point, the input data width is fixed at 32 bits and the phase factor width can be set to 24 or 25 bits depending on the noise performance required and available resources.
• Scaling Options : Three options are available, for all architectures:
° Unscaled
- All integer bit growth is carried to the output. This can use more FPGA resources.
° Scaled
- A user-defined scaling schedule determines how data is scaled between FFT stages.
° Block Floating-Point
- The core determines how much scaling is necessary to make best use of available dynamic range, and reports the scaling factor as a block exponent.
• Control Signals : Clock Enable ( aclken ) and Synchronous Clear ( aresetn ) are optional pins. Synchronous Clear overrides Clock Enable if both are selected. If an option is not selected, some logic resources can be saved and a higher clock frequency might be attainable.
• Optional Output Fields : XK_INDEX is an optional field in the Data Output Channel . OVFLO is an optional field in both the Data Output channel and Status Channel .
• Throttle Schemes : Select trade-off between performance and data timing requirements. Realtime mode typically gives a smaller and faster design, but has strict constraints on when data must be provided and consumed. Non-Realtime mode has no such constraints, but the design might be larger and slower. See Controlling the FFT Core for more details.
• Rounding Modes : At the output of the butterfly, the LSBs in the datapath need to be trimmed. These bits can be truncated or rounded using convergent rounding, which is an unbiased rounding scheme. When the fractional part of a number is equal to exactly one-half, convergent rounding rounds up if the number is odd, and rounds down if the number is even. Convergent rounding can be used to avoid the DC bias that would otherwise be introduced by truncation after the butterfly stages. Selecting this option increases slice usage and yields a small increase in transform time due to additional latency.
• Output Ordering : Output data selections are either Bit/Digit Reversed Order or Natural Order. The Radix-2 based architectures (Pipelined Streaming I/O, Radix-2 Burst I/O and Radix-2 Lite Burst I/O) offer bit-reversed ordering, and the Radix-4 based architecture (Radix-4 Burst I/O) offers digit-reversed ordering. For the Pipelined Streaming I/O architecture, selecting natural order output ordering results in an increase in memory used by the core. For Burst I/O architectures, selecting natural order output increases the overall transform time because a separate unloading phase is required.
° Cyclic Prefix Insertion can be selected if the output ordering is Natural Order. Cyclic Prefix Insertion is available for all architectures, and is typically used in OFDM wireless communications systems.