Pipelined Streaming I/O Architecture - 9.1 English

PG109 Fast Fourier Transform LogiCORE IP Product Guide

Document ID
PG109
Release Date
2022-05-04
Version
9.1 English

For the Pipelined Streaming I/O architecture, consider every pair of adjacent Radix-2 stages as a group. That is, group 0 contains stage 0 and 1, group 1 contains stage 2 and 3, and so on. The value of the SCALE_SCH field is also used as pairs of bits [... N4, N3, N2, N1, N0]. Each pair represents the scaling value for the corresponding group of two stages. Groups are computed starting with group 0 as the two LSBs. In each group, the data can be shifted by 0, 1, 2, or 3 bits which corresponds to SCALE_SCH values of 00, 01, 10, and 11. For example, when N = 1024, [10 10 00 01 11] translates to a right shift by 3 for group 0 (stages 0 and 1), shift by 1 for group 1 (stages 2 and 3), no shift for group 3 (stages 4 and 5), a shift of 2 in group 3 (stages 6 and 7), and a shift of 2 for group 4 (stages 8 and 9). The conservative schedule SCALE_SCH = [10 10 10 10 11] completely avoids overflows in the Pipelined Streaming I/O architecture. When the point size is not a power of 4, the last group only contains one stage, and the maximum bit growth for the last group is one bit. Therefore, the two MSBs of the scaling schedule can only be 00 or 01. A conservative scaling schedule for N = 512 is SCALE_SCH = [01 10 10 10 11].

The initial value and reset value of the FWD_INV field is forward = 1. The scaling schedule is set to 1/N . That translates to [10 10 10 10... 10] for the Radix-4, Burst I/O and Pipelined Streaming I/O architectures, and [01 01... 01] for the Radix-2 architectures. The core uses the (2*number of stages) LSBs for the scaling schedule. So, when the point size decreases, the leftover MSBs are ignored. However, all bits are programmed into the core and are used in later transforms if the point size increases.