The Implementation tab is used to specify memory and optimization options in a similar way to page 3 of the Vivado IDE.
• Number of stages using block RAM : Specifies the number of stages for the Pipelined Streaming I/O architecture that uses block RAM for data and phase factor storage. As dynamic list boxes are not offered with the System Generator GUI, this option displays the full range (0 to 11) selection, but allows you to select only valid values as visible in the Vivado IDE.
• FPGA Area Estimation : See the System Generator for DSP User Guide (UG640) [Ref 11] for detailed information about this option.