The core starts to process a frame as soon as a) the upstream master asks it to by supplying data to process, and b) when it is able to. The chosen architecture and cyclic prefix insertion are the major configuration options that affect when the core is able to process a new frame.
The following timing diagrams are generalizations of actual behavior used to show the broad phases the core moves through when processing frames, and how these phases can (or cannot) overlap. The lengths of the various phases are not to scale, and the processing time might be much longer than the time required to input or output a frame.
In particular, the behavior of TREADY on the input data channel is not fully accurate because the Data Input channel buffers the data (16 symbols in Non-Realtime mode and 1 symbol in Realtime mode). However, this data waits in the buffer until the FFT processing core is ready for it. The Data Input channel TREADY in these diagrams is used as an indication of when the FFT processing core wants data rather than when the AXI channel (with its buffer) wants data.