If the aresetn pin is present on the core, driving the pin Low causes all output pins, internal counters, and state variables to be reset to their initial values. The initial values described in Table: Synchronous Clear Reset Values for Configuration Information are also the default values that the circuit adopts on power-on, regardless of whether the core is configured for aresetn or not. All pending load processes, transform calculations, and unload processes stop and are re-initialized. NFFT is set to the largest FFT point size permitted (the Transform Length value set in the Vivado ® Integrated Design Environment (IDE)). The scaling schedule is set to 1/N. For the Radix-4 Burst I/O and Pipelined Streaming I/O architectures with a non-power-of-four point size, the last stage has a scaling of 1, and the rest have a scaling of 2. See Table: Synchronous Clear Reset Values for Configuration Information .
The aresetn pin takes priority over aclken . If aresetn is asserted, reset occurs regardless of the value of aclken . A minimum aresetn active pulse of two cycles is required, because the signal is internally registered for performance. A pulse of one cycle resets the core, but the response to the pulse is not in the cycle immediately following.