This event signal is asserted for a single clock cycle when the core sees s_axis_data_tlast High on any incoming data sample that is not the last one in a frame. This shows a configuration mismatch between the core and the upstream data source with regard to the frame size, and indicates that the upstream data source is configured to a smaller point size than the core. This is only calculated when the core starts processing a frame, so the event can lag the unexpected High on s_axis_data_tlast by a large number of clock cycles.
If there are multiple unexpected highs on s_axis_data_tlast for a frame, then this is asserted for each of them.