This register defines a delay in
M_AXIS_ACLK clock cycles after
each output packet. This register is a write-only register. Issuing a read request
has no effect, and undefined data is read.
This delay is primarily intended to avoid downstream FIFO overflow, which can occur for AXI4-Stream connections that do not implement a ready signal, such as the Zynq® Fabric Trace Monitor interface (see the Zynq-7000 SoC Technical Reference Manual (UG585)).
|31 - 8||Reserved||N/A||0||Reserved|
|7 - 0||Packet Delay||W||0x00||Delay in M_AXIS_ACLK clock cycles between each word in the output packet, 0 - 255.|