S_AXI_ACLK input is only used when the
JTAG-based UART or Debug register access is enabled, and AXI4-Lite slave interconnect is used, or when BSCAN is disabled. Then it should
normally be set to the same clock as the interconnect.
M_AXI_ACLK input is used when JTAG
Memory Access is enabled, and AXI4 master interconnect
and/or LMB master interface is used. Then it must be set to the same clock as the interconnect
and LMB interface. Different clocks for AXI4 and LMB is
not supported in this case. The
M_AXI_ACLK input is also used
when AXI4 master trace output is selected. Then it must be
set to the same clock as the interconnect. It can be asynchronous to other clocks. The LMB
interface is not used in this case.
M_AXIS_ACLK is used when AXI4-Stream trace output is selected. Then it should be set to the
same clock as the AXI4-Stream slave the trace interface is
connected to. It can be asynchronous to all other clocks.
TRACE_CLK input clock is used when
external trace output is selected. This clock could be generated on-chip or be derived from an
off-chip source. It can be asynchronous to all other clocks. The nominal clock frequency is
200 MHz. If another clock frequency is used, the parameter
C_TRACE_CLK_FREQ_HZ must be manually changed accordingly.
TRACE_CLK_OUT output clock is a divided
by two version of
TRACE_CLK, to provide a clock that toggles
on both edges of the
TRACE_CTL data and control outputs. To create a sample point at a stable point of
the outputs, a 90° phase shift is nominally added to the
TRACE_CLK_OUT clock. The phase shift can be adjusted manually with the parameter
C_TRACE_CLK_OUT_PHASE if necessary.
For more details on the
TRACE_CLK_OUT clocking requirements, see the ().
Apart from the JTAG-based UART, Debug register access, JTAG memory access, and trace output, the MDM core is clocked from the BSCAN when it is enabled, with a clock frequency determined by the JTAG connection.
When programming a System ACE™ device, the MDM core clock must be at least twice as fast as the System ACE tool controller clock for the ELF file to load correctly.