Debug_SYS_Rst output can be used to
reset the entire embedded system on the device, including all processors and peripherals.
Normally it is connected to a proc_sys_reset IP core. The
System Debugger (XSDB) command
be used to activate the signal.
The Debug bus connecting each individual
processor handled by the MDM core, has
Dbg_Rst reset signal. This signal can be used to just reset an individual
processor. The XSDB command
rst -processor can be used to activate the signal
for the selected target processor. The signal is not available when AXI parallel debug is
S_AXI_ARESETN input is only used when the JTAG-based UART or Debug
register access is enabled, and AXI4-Lite slave interconnect is used, or
when BSCAN is disabled. Then it should normally be set to the same reset as the
M_AXI_ARESETN input is used when JTAG
Memory Access is enabled, and AXI4 master interconnect
and/or LMB master interface is used. Then it must use the same reset as the interconnect. A
corresponding reset for LMB must also be used. The
M_AXI_ARESETN input is
also used when AXI4 master trace output is selected. Then
it must use the same reset as the interconnect. The LMB interface is not used in this
M_AXIS_ARESETN is used when AXI4-Stream trace output
is selected. Then it should use the same reset as the AXI4-Stream slave the
trace interface is connected to.