The simulation debug flow for Mentor Graphics Questa Advanced Simulator is illustrated in the following figure. A similar approach can be used with other simulators.
- Check for the latest supported versions of Questa Advanced Simulator in the Xilinx® Design Tools: Release Notes Guide. Is this version being used? If not, update to this version.
- If using Verilog, do you have a mixed mode simulation license? If not, obtain a mixed-mode license.
- Ensure that the proper libraries are compiled and mapped. In the Vivado® Design Suite can be used to define the libraries.
- Have you associated the intended software program for the MicroBlaze™ processor with the simulation? Use the command in Vivado Design Suite.
- When observing the traffic on the interfaces connected to the MDM core,
see the timing in the relevant specification:
- For AXI4 and AXI4-Lite, see the AMBA® AXI and ACE Protocol Specification.