Another example use case, shown in the following figure, is a set of
accelerators connected through the System Cache core to the ACE port on a Zynq UltraScale+ MPSoC. To fully take advantage of the
System Cache, AXI transactions from the accelerators should be set up as Write-Back
memory type (
AWCACHE), preferably Write-back Read and Write-allocate. If it is not
possible to directly control this from an accelerator, it is possible to override some
AxCACHE function through parameters such as
C_Sx_AXI_GEN_FORCE_WRITE_ALLOCATE on a per port
basis. This override functionality is available on all ports including the optimized
It is possible to connect one or more MicroBlaze processor caches to the optimized ports, but they will not be cache coherent with the Zynq UltraScale+ MPSoC Processing System (PS) so manual cache maintenance with WIC and WDC type instructions is needed to observe data.
Example parameters for the System Cache core in this kind of
configuration can be found in the following table.
Sx_AXI_GEN_* should be configured for all active ports.
|C_NUM_GENERIC_PORTS||2 or more|
C_Sx_AXI_GEN_PROHIBIT_WRITE_ALLOCATE parameters are cleared by default and
need to be set to disable allocation on Write Miss. This is not backwards compatible
with earlier System Cache versions.