ATS/ATC error handling expands on the PCIe, Requester and Completer AXI4-Stream, error handling and extends it to full AER support. Generated AER messages and created error logs depend on the configuration defined by control registers.
Internal ATC memory structures are protected by optional parity. All internal ATC memory parity errors are reported as internal ATC correctable errors via PER logging, which is propagated in CCIX configurations.
- Protocol errors reported via the Advanced Error Reporting Extended
- Unsupported Request (UR), Completer Abort (CA), or Unexpected Completion: AER is propagated by the ATS interface
- AXI4-Stream parity error: When parity check is enabled, AER is propagated by the ATS interface and the TLP is aborted
- Malformed TLP detected by the PCIe core: AER is reported by the core and the ongoing translation results in Decode Error on the generic AXI port BRESP
- Illegal TAG usage, unsuccessful or erroneous completions detected by the PCIe core: AER is reported by the core and the ongoing translation results in Decode Error on the generic AXI port BRESP
- Requester channel timeout detected by the PCIe core: AER is reported by the core
- Protocol Completer channel timeouts: AER is propagated by the ATS interface and the ongoing translation results in Decode Error on the generic AXI port BRESP
- Protocol Error not reported via AER:
- Receiver overflow: Error should avoided by configuration and when full or not ready the ATS interface does not accept additional data on the AXI4-Stream interface
- ECRC Check Failed: ECRC is not supported and System Cache must be configured with the TD bit cleared
- Header Discontinue, Poisoned TLP Received: Transaction is aborted and no AER is propagated by the ATS interface
The ATS/ATC error handling is enabled with the
C_ATS0_CQ_CC_ENABLE_AER parameter for Completer channels and
C_ATS0_RQ_RC_ENABLE_AER for Requester channels.
When ATS AER handling is enabled a detected error will be logged and propagated to the PCIe Host and the Cmd/Cpl (header) and/or Payload (data) affected will be discarded.
In case CA/UR, Sequence and TLP incompleteness are detected on the RC channel, errors signaled over AXI4-Stream are logged and reported, but error handling relies on the PCIe core reporting of AER external to System Cache for complementary error logs.
The ATC integrity error handling feature is controlled by the
C_ENABLE_INTEGRITY, also used
for all other System Cache integrity functionality.
In case of ATC integrity error detection, caused by a Single Event Upset (SEU) or by integrity function fault injection, the affected ATC table entry is silently invalidated to avoid undetectable multiple error accumulation in the memory.
ATC Table look-up, in case of an ATC TLB miss, blocks any attempt to use table entries with parity errors. The automatic background scrubbing or manually initiated scrubbing then removes any pending errors from the ATC Table, with silent invalidation.
Also note that any normal Host TA commanded invalidation, for any address range, causes pending errors to be removed.
Integrity error detection and removal is logged and reported via PER.
ATC integrity handling uses the same structure on CHI as for CCIX, with PER Log but without the PER message propagation.
With CHI, the interrupt event notifies the software error manager to poll the PER log
An ATC integrity error is correctable on system level, since the PCIe host TA holds all translations cached by the ATC Table. Any invalidation due to an integrity error will cause a new ATS TA request.
See the PCI Express® Base Specification for the AER structure definition, and CCIX® Base Specification for the PER message definition.