Backend CCIX and CHI Registers - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

Backend CCIX and CHI Registers

In the nominal use case the registers below are handled by firmware executing in the MicroBlaze processor sub-system, and there is nothing the user needs to handle.

Fields denoted with FW: in the descriptions below are updated by the firmware.

Unused CCIX registers are reserved in CHI context, and will return Reserved default value if read.

Table 1. Backend CCIX Address Map
Offset Register Name Access Format Description
0x1_A200 CCIXCCSI0 R 32 Primary Port 0 Common Capability & Status I
0x1_A204 CCIXCCSII0 R 32 Primary Port 0 Common Capability & Status II
0x1_A208 CCIXCCSIII0 R 32 Primary Port 0 Common Capability & Status III
0x1_A210 CCIXCCI0 R/W 32 Primary Port 0 Common Control I
0x1_A214 CCIXCCII0 R/W 32 Primary Port 0 Common Control II
0x1_A218 CCIXDEVECS0 R/W 32 CCIX Device Error Control & Status
0x1_A21C CCIXSCPCIE0 R/W 32 Primary Port 0 SC PCIe & CCIX Common
0x1_A280 CCIXCSI0 R 32 Port 0 Capability & Status I
0x1_A284 CCIXCSII0 R 32 Port 0 Capability & Status II
0x1_A288 CCIXCSIII0 R 32 Port 0 Capability & Status III
0x1_A290 CCIXCS00 R 32 Port 0 Error Control & Status 0
0x1_A294 CCIXCS10 R 32 Port 0 Error Control & Status 1
0x1_A298 CCIXCI0 R/W 32 Port 0 Control I
0x1_A29C CCIXTPIDM0 R/W 32 Port 0 Source TransportID Map
0x1_A300 CCIXL0TXS0 R 64 Port 0 Link 0 System Cache Tx Status
0x1_A380 CCIXL0RXS0 R 64 Port 0 Link 0 System Cache Rx Status
0x1_A680 CCIXL0BFCV0 R/W 64 Port 0 Link 0 BFCV0 + BFCV1
0x1_B000 CCIXL0CI0 R/W 32 Port 0 Link 0 Control I
0x1_B004 CCIXL0CII0 R/W 32 Port 0 Link 0 Control II
0x1_B008 CCIXL0CIII0 R/W 32 Port 0 Link 0 Control III
0x1_B00C CCIXL0CIV0 R/W 32 Port 0 Link 0 Control IV
0x1_B010 CCIXL0ECS00 R/W 32 Port 0 Link 0 Error Control & Status 0
0x1_B014 CCIXL0ECS01 R/W 32 Port 0 Link 0 Error Control & Status 1
0x1_B018 CCIXL0DTPIDM0 R/W 32 Port 0 Link 0 Destination TransportID Map
0x1_B01C CCIXL0PLSPEC0 R/W 32 Port 0 Link 0 SC Port/Link Specific
0x1_B200 CCIXLCSI0 R 32 Port 0 Link Capability and Status I
0x1_B204 CCIXLCSII0 R 32 Port 0 Link Capability and Status II
0x1_B208 CCIXLCSIII0 R 32 Port 0 Link Capability and Status III
0x1_B20C CCIXLCSIV R 32 Port 0 Link Capability and Status IV
0x1_B300 CCIXTRA0CS1 R 32 RA0 Capability and Status 1
0x1_B304 CCIXRA0CI R/W 32 RA0 Control I
0x1_B310 CCIXRA0ECS0 R/W 32 RA0 Error Control & Status 0
0x1_B314 CCIXRA0ECS1 R/W 32 RA0 Error Control & Status 1
0x1_B318 CCIXRA0SCSPE R/W 64 SC RA0 Specific
Table 2. Backend CHI Address Map
Offset Register Name Access Format Description
0x1_A300 CCIXL0TXS0 R 64 Port 0 Link 0 System Cache Tx Status
0x1_A380 CCIXL0RXS0 R 64 Port 0 Link 0 System Cache Rx Status
0x1_B01C CCIXL0PLSPEC0 R/W 32 Port 0 Link 0 SC Port/Link Specific
0x1_B300 CCIXTRA0CS1 R 32 RA0 Capability and Status 1
0x1_B304 CCIXRA0CI R/W 32 RA0 Control I
0x1_B310 CCIXRA0ECS0 R/W 32 RA0 Error Control & Status 0
0x1_B314 CCIXRA0ECS1 R/W 32 RA0 Error Control & Status 1
0x1_B318 CCIXRA0SCSPE R/W 64 SC RA0 Specific

Primary Common Capabilities & Status I (DVSEC) Register

Figure 1. Primary Common Capabilities & Status I (DVSEC) Register
Table 3. Primary Common Capabilities & Status I (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31:24 DevIDStat 0 R FW: Device ID Status
23:22 ComnVersionCap 0 R FW: Common Version Capability
21:3       Reserved
2:0 MultiportDevCap 0 R MultiPort Device Capability

Primary Common Capabilities & Status II (DVSEC) Register

Figure 2. Primary Common Capabilities & Status II (DVSEC) Register
Table 4. Primary Common Capabilities & Status II (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31       Reserved
30:28 DevRdyTimeScale 0 R FW: Readiness Time Scale
27:19 DevRdyTimeValue 0 R FW: Readiness Time Value
18:16       Reserved
15 DeviceHWQACKCap 0 R CCIX Device HW QACK Capability
14 DeviceQACK 0 R CCIX Device HW QACK
13:10       Reserved
9 SAMAlignCap 0 R SAM Alignment Capability
8 SoftwareServicePortalCap 0 R FW: CCIX Software Service Portal Capability
7 MultiHopPortAggrCap 0 R Multi-Hop Port Aggregation Capability
6:4 AddrWidthCap 0 R Address Width Capability
3 CacheLineSizeCap 0 R Cache Line Size Capability
2 PortAggCap 0 R Port Aggregation Capability
1 PartialCacheStatesCap 0 R Partial Cache State Capability
0 DevDiscRdyStat 1 R Device Discovery Register Status

Primary Common Capabilities & Status III (DVSEC) Register

Figure 3. Primary Common Capabilities & Status III (DVSEC) Register
Table 5. Primary Common Capabilities & Status III (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
63:0       Reserved

Primary Common Control I (DVSEC) Register

Figure 4. Primary Common Control I (DVSEC) Register
Table 6. Primary Common Control I (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31:24 DevIDCntl 0 R/W FW: DIDC
23:22       Reserved
21:16 ErrAgentID 0 R/W Error Agent ID
15:9       Reserved
8 SoftwareServicesPortEnable 0 R/W FW: Software Service Portal Enable
7 HSAMTblVal 0 R/W HSAM Table Valid
6 RSAMTblVal 0 R/W RSAM Table Valid
5 IDMTblVal 0 R/W FW: IDM Table Valid
4 PortAggEnable 0 R/W Port Aggregation Enable
3       Reserved
2 MeshTopologyEnable 0 R/W Mesh Topology Enable
1 PrimaryPortEnable 0 R/W Primary Port Enable
0 DevEnable 0 R/W Device Enable

Primary Common Control II (DVSEC) Register

Figure 5. Primary Common Control II (DVSEC) Register
Table 7. Primary Common Control II (DVSEC) Bit Definitions
Bits Name Reset Value Access Description
31:21 QUACKTIMEValue 0 R/W QUACK Time Value
20 QUACKTimeScale 0 R/W QUACK Time Scale
19:15       Reserved
14 DeviceQREQ 0 R/W CCIX Device QREQ
13:7       Reserved
6:4 AddrWidthEnable 0 R/W Address Width Enable
3 CacheLineSizeEnable 0 R/W Cacheline Size Enable
2       Reserved
1 PartialCacheStatesEnable 0 R/W Partial Cache State Enable
0       Reserved

CCIX Device Error Control & Status Register

Figure 6. CCIX Device Error Control & Status Register
Table 8. CCIX Device Error Control & Status Bit Definitions
Bits Name Reset Value Access Description
31:1       Reserved
0 EN 0 R/W Error Reporting Enable

Primary PCIe & CCIX Common Register

Figure 7. Primary PCI & CCIX Common Register
Table 9. Primary PCI & CCIX Common Bit Definitions
Bits Name Reset Value Access Description
31:28       Reserved
27 MSDA 0 R/W Move to SD Allowed
26:24 TC 0 R/W TC
23:16 Tag 0 R/W Tag
15:0 VendorID 0 R/W Vendor ID

Port Capability & Status I Register

Figure 8. Port Capability & Status I Register
Table 10. Port Capability & Status I Bit Definitions
Bits Name Reset Value Access Description
31:27 PortÍD 0 R CCIX Port ID
26:19       Reserved
18:13 NumPSAMEntryCap 0x2 R FW: Number of PSAM Entries Capabilities
12:7 NumLinksCap 0x1 R Number of Links Capability
6       Reserved
5 PortToPortFwdingCap 0 R Port-to-Port Forward Capability
4 PortHWQACKCap 0 R Port HW QACK Capability
3 PortQAck 0 R Port QUACK
2       Reserved
1 PktHdrTypeCap 0 R Package Header Type Capability (Optimized)
0 PortDiscRdyStat 1 R CCIX Port Discover Status

Port Capability & Status II Register

Figure 9. Port Capability & Status II Register
Table 11. Port Capability & Status II Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 PortAggVctr 0 R FW: Aggregation with PortID15-PortID0

Port Capability & Status III Register

Figure 10. Port Capability & Status III Register
Table 12. Port Capability & Status III Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 PortFwdingvVctr 0 R FW: Forwarding to PortID15-PortID0

Port Error Control & Status 0 Register

Figure 11. Port Error Control & Status 0 Register
Table 13. Port Error Control & Status 0 Bit Definitions
Bits Name Reset Value Access Description
31:4       Reserved
3:2 Dis 0 R/W PER Disable
1:0 Sta 0 R/W Error Status

Port Error Control & Status 1 Register

Figure 12. Port Error Control & Status 1 Register
Table 14. Port Error Control & Status 1 Bit Definitions
Bits Name Reset Value Access Description
31:26       Reserved
25:16 PerTypeMask 0 R/W PER Type Mask
15:14       Reserved
13:8 SevReportMask 0 R/W Severity Reporting Mask
7:6       Reserved
5:0 SevLogMask 0 R/W Severity Logging Mask

Port Control I Register

Figure 13. Port Control I Register
Table 15. Port Control I Bit Definitions
Bits Name Reset Value Access Description
31:19       Reserved
18:13 NumPSMAEntryEnable 0 R/W FW: Number of PSAM Entries Enable
12:7 NumLinksEnable 0 R/W Number of Links Enable
6:4       Reserved
3 PortQREQ 0 R/W Port QREQ
2       Reserved
1 PktHdrTypeEnable 0 R/W Optimized Packet Header Type Enable
0 PortEnable 0 R/W Port Enable

Port Source Transport ID Map Register

Figure 14. Port Source Transport ID Map Register
Table 16. Port Source Transport ID Map Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 RequestorID 0 R/W Requestor ID

Port Link Tx Status Register

Figure 15. Port Link Tx Status Register
Table 17. Port Link Tx Status Bit Definitions
Bits Name Reset Value Access Description
63:52       Reserved
51:42 TxTLCL 0 R

CCIX: CXS Transaction Layer Credit Level available for use /

CHI: Reserved

41:32 TxMISCCL 0 R

CCIX: Misc Credit Level available for use /

CHI: TX Rsp Credit Level available for use

31:30       Reserved
29:20 TxDATCL 0 R

CCIX: Data Credit Level available for use /

CHI: TX Data Credit Level available for use

19:10 TxSNPCL 0 R

CCIX: Snoop Credit Level available for use /

CHI: RX Snoop Credit Level available for use

9:0 TxMEMCL 0 R

CCIX: Memory Request Credit Level available for use /

CHI: TX Req Credit Level available for use

Port Link Rx Status Register

Figure 16. Port Link Rx Status Register
Table 18. Port Link Rx Status Bit Definitions
Bits Name Reset Value Access Description
63 RxTLActReq 0 R

CCIX: CXS0_ACTIVE_REQ_RX value /

CHI: M0_CHI_RXLINKACTIVEREQ value

62 TxTLActAck 0 R

CCIX: CXS0_ACTIVE_ACK_TX value /

CHI: M0_CHI_TXLINKACTIVEACK value

61 TxTLDeActHint 0 R

CCIX: CXS0_DEACT_HINT_TX value /

CHI: RXLINK goes to Deactivate state

60 ChiSysCoAck 0 R

CCIX: Reserved /

CHI: M0_CHI_SYSCOACK value

59 ChiTxSActive 0 R

CCIX: Reserved /

CHI: M0_CHI_TXSACTIVE value

58 ChiRxSActive 0 R

CCIX: Reserved /

CHI: M0_CHI_RXSACTIVE value

57:52       Reserved
51:42 RxTLCL 0xF R

CCIX: CXS Transaction Layer Credit Level that can be granted /

CHI: Reserved

41:32 RxMISCCL 0 R

CCIX: Misc Credit Level that can be granted /

CHI: RX Rsp Credit Level that can be granted

31:30       Reserved
29:20 RxDATCL 0 R

CCIX Data Credit Level that can be granted /

CHI: RX Data Credit Level that can be granted

19:10 RxSNPCL 0 R

CCIX: Snoop Credit Level that can be granted /

CHI: RX Snoop Credit Level that can be granted

9:0 RxMEMCL 0 R

CCIX: Memory Request Credit Level that can be granted /

CHI: Reserved

Port Link BFCV0+BFCV1 Register

Figure 17. Port Link BFCV0+BFCV1 Register
Table 19. Port Link BFCV0+BFCV1 Bit Definitions
Bits Name Reset Value Access Description
63:32 BCastFwdCntlVctr1 0 R/W FW: Broadcast Forward Control Vector1
31:0 BCastFwdCntlVctr0 0 R/W FW: Broadcast Forward Control Vector 0

Port Link Control I Register

Figure 18. Port Link Control I Register
Table 20. Port Link Control I Bit Definitions
Bits Name Reset Value Access Description
31:11       Reserved
10 LinkEntryAddrType 0 R/W FW: Link Entry Address Type
9:7 MaxPktSizeEnable 0 R/W Max Package Size Enable
6 NoCompAckEnable 0 R/W NoCompAck Enable
5:4       Reserved
3 LinkQREQ 0 R/W Link Quiescent Request
2 MsgPackingEnable 0 R/W Message Packing Entry
1 LinkCreditSendEnable 0 R/W CCIX Link Credit Send Enable
0 LinkEnable 0 R/W CCIX Link Enable

Port Link Control II Register

Figure 19. Port Link Control II Register
Table 21. Port Link Control II Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MaxDatReqCreditEnable 0 R/W Maximum Data Request Credit Enable
19:10 MaxSnpReqCreditEnable 0 R/W Maximum Snoop Request Credit Enable
9:0 MaxMemReqCreditEnable 0 R/W Maximum Memory Request Credit Enable

Port Link Control III Register

Figure 20. Port Link Control III Register
Table 22. Port Link Control III Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MinDatReqCreditEnable 0 R/W Minimum Data Request Credit Enable
19:10 MinSnpReqCreditEnable 0 R/W Minimum Snoop Request Credit Enable
9:0 MinMemReqCreditEnable 0 R/W Minimum Memory Request Credit Enable

Port Link Control IV Register

Figure 21. Port Link Control IV Register
Table 23. Port Link Control IV Bit Definitions
Bits Name Reset Value Access Description
31:20       Reserved
19:10 MinMiscReqCreditEnable 0 R/W Minimum Request Credit Enable
9:0 MaxMiscReqCreditEnable 0 R/W Maximum Misc Request Credit Enable

Port Link Error Control & Status 0 Register

Figure 22. Port Link Error Control & Status 0 Register
Table 24. Port Link Error Control & Status 0 Bit Definitions
Bits Name Reset Value Access Description
31:4       Reserved
3:2 Dis 0 R/W PER Disable
1:0 Sta 0 R/W Error Status

Port Link Error Control & Status 1 Register

Figure 23. Port Link Error Control & Status 1 Register
Table 25. Port Link Error Control & Status 1 Bit Definitions
Bits Name Reset Value Access Description
31:26       Reserved
25:16 PerTypeMask 0 R/W PER Type Mask
15:14       Reserved
13:8 SevReportMask 0 R/W Severity Reporting Mask
7:6       Reserved
5:0 SevLogMask 0 R/W Severity Logging Mask

Port Link Destination TransportID Map Register

Figure 24. Port Link Destination TransportID Map Register
Table 26. Port Link Destination TransportID Map Bit Definitions
Bits Name Reset Value Access Description
31:16       Reserved
15:0 DestTransportID 0 R/W Destination Transport ID

SC Specific Port Link Specific Register

Figure 25. SC Specific Port Link Specific Register
Table 27. SC Specific Port Link Specific Bit Definitions
Bits Name Reset Value Access Description
31:22       Reserved
21 FTXLACT 0 R/W Reserved (Force TX Link activation)
20 TLDEHI 0 R/W

CCIX: Transaction Layer Deactivation Hint /

CHI: Reserved

19 NRRA 0 R/W Reserved (No Remote RA)
18 ENCOHCHI 0 R/W

CCIX: Reserved /

CHI: Enable coherency by using the System Coherency handshake

17 SNRRA 0 R/W Reserved (Single Remote RA)
16 PLRSTC 0 R/W

CCIX: Protocol Layer Reset Credits /

CHI: Reserved

15 PLRETC 0 R/W

CCIX: Protocol Layer Return Credits /

CHI: Reserved

14 PLEXCC 0 R/W

CCIX: Protocol Layer Exchange Credits /

CHI: Reserved

13 TLRSTC 0 R/W Transaction Layer Reset Credits
12 TLRETC 0 R/W Transaction Layer Return Credits
11 TLEXCC 0 R/W Transaction Layer Exchange Credits
10 TLACTC 0 R/W Transaction Layer Activate Connection
9:6 MCL 0 R/W Reserved (Max Chain Length)
5:0 TGTID 0 R/W

CCIX: TgtID, when Sending Credit Exchange /

CHI: Reserved

Port Link Capability & Status I Register

Figure 26. Port Link Capability & Status I Register
Table 28. Port Link Capability & Status I Bit Definitions
Bits Name Reset Value Access Description
31:10       Reserved
9:7 MaxPktSizeCap 0 R Max Package Size Capability
6 NoCompAckCap 0 R NoCompAck Capability
5       Reserved
4 LinkHWQACKCap 0 R Link’s Hardware Quiesce Acknowledgment Capability
3 LinkQACK 0 R Link’s Quiesce Acknowledgment status
2 MsgPackingCap 0 R Message Packing Capability
1 LinkCreditType 0 R CCIX Link Credit Type
0 LinkDiscRdyStat 1 R CCIX Link Discovery Status

Port Link Capability & Status II Register

Figure 27. Port Link Capability & Status II Register
Table 29. Port Link Capability & Status II Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MaxDatReqSendCap N 1 R Maximum Data Request Send Capability
19:10 MaxSnpReqSendCap M 2 R Maximum Snoop Request Send Capability
9:0 MaxMemReqSendCap N 1 R Maximum Memory Request Send Capability

Port Link Capability & Status III Register

Figure 28. Port Link Capability & Status III Register
Table 30. Port Link Capability & Status III Bit Definitions
Bits Name Reset Value Access Description
31:30       Reserved
29:20 MaxDatReqRcvCap N 1 R Maximum Data Request Receive Capability
19:10 MaxSnpReqRcvCap M 2 R Maximum Snoop Request Receive Capability
9:0 MaxMemReqRcvCap N 1 R Maximum Memory Request Receive Capability

Port Link Capability & Status IV Register

Figure 29. Port Link Capability & Status IV Register
Table 31. Port Link Capability & Status IV Bit Definitions
Bits Name Reset Value Access Description
31:20       Reserved
19:10 MaxMiscReqRcvCap 0x10 R Maximum Misc Request Send Capability
9:0 MaxMiscReqSendCap 0x10 R Maximum Misc Request Receive Capability

RA Capability & Status I Register

Figure 30. RA Capability & Status I Register
Table 32. RA Capability & Status I Bit Definitions
Bits Name Reset Value Access Description
31 RACacherFlushStat 0 R Cache Flush Status
30:28 CacheFlushTimeScale 0 R Cache Flush Completion Time Scale
27:19 CacheFlushTimeValue 0 R Cache Flush Completion Time Value
18 RAPreciseSnpRespCap 0 R RA Precise Snp Resp Capability
17:5       Reserved
4 RAHWQUACKCap 0 R RA HW QUACK Capability
3 RAQUACK 0 R RA QACK
2:1       Reserved
0 RADiscRdyStat 1 R Request Agent Discovery Status

RA Control I Register

Figure 31. RA Control I Register
Table 33. RA Control I Bit Definitions
Bits Name Reset Value Access Description
31:26 RAID 0 R/W Request Agent ID
25:19       Reserved
18 RAWriteEvictFullHintCntl 0 R/W RA WriteEvictFull Hint Control
17 RAEvictHintCntl 0 R/W RA Evict Hint Control
16       Reserved
15 RACacheFlushEnable 0 R/W Cache Flush Enable
14 RACacheEnable 0 R/W Cache Enable
13:4       Reserved
3 RAQREQ 0 R/W RA QREQ
2       Reserved
1 RASnpRspEnable 0 R/W RA Snoop Response Enable
0 RAEnable 0 R/W Request Agent Enable

RA Error Control Status 0 Register

Figure 32. RA Error Control Status 0 Register
Table 34. RA Error Control Status 0 Bit Definitions
Bits Name Reset Value Access Description
31:4       Reserved
3:2 DIS 0 R/W PER Disable (LogDis and Dis)
1:0 STA 0 R/W Error Status (Sta)

RA Error Control Status 1 Register

Figure 33. RA Error Control Status 1 Register
Table 35. RA Error Control Status 1 Bit Definitions
Bits Name Reset Value Access Description
31:26       Reserved
25:16 PerTypeMask 0 R/W PER Type Mask
15:14       Reserved
13:8 SevReportMask 0 R/W Severity Reporting Mask
7:6       Reserved
5:0 SevLogMask 0 R/W Severity Logging Mask

RA System Cache Specific Register

Figure 34. RA System Cache Specific Register
Table 36. RA System Cache Specific Bit Definitions
Bits Name Reset Value Access Description
63:45       Reserved
44 SNPNSDFWDPASS 0 R/W SnpNSDFwd Pass Dirty
43 SNPNSDFWDKEEP 0 R/W SnpNSDFwd Keep Line
42 SNPSHFWDHOME 0 R/W SnpSharedFwd Dirty Home, move dirty data to Home instead of requesting RN
41 SNPSHFWDPASS 0 R/W SnpSharedFwd Pass Dirty
40 SNPSHFWDKEEP 0 R/W SnpSharedFwd Keep Line
39 SNPCLFWDPASS 0 R/W SnpCleanFwd Pass Dirty
38 SNPCLFWDKEEP 0 R/W SnpCleanFwd Keep Line
37 SNPOFWDPASS 0 R/W SnpOnceFwd Pass Dirty
36 SNPOFWDKEEP 1 R/W SnpOnceFwd Keep Line
35:32 QoS 0x10 R/W Quality of Service
31:26       Reserved
25 SNPCLNSHKEEP 0 R/W SnpCleanShared Keep Line
24 SNPTOSCKEEP 0 R/W SnpToSC Keep Line
23 SNPNSDPASS 0 R/W SnpNSD Pass Dirty
22 SNPNSDKEEP 0 R/W SnpNSD Keep Line
21 SNPSHPASS 0 R/W SnpShared Pass Dirty
20 SNPSHKEEP 0 R/W SnpShared Keep Line
19 SNPCLPASS 0 R/W SnpClean Pass Dirty
18 SNPCLKEEP 0 R/W SnpClean Keep Line
17 SNPOPASS 0 R/W SnpOnce Pass Dirty
16 SNPOKEEP 1 R/W SnpOnce Keep Line
15:11       Reserved
10:0 RNFID 0 R/W RN-F NodeID (CHI only)