This section includes information about using Xilinx® tools to customize and generate the core in the Vivado® Design Suite.
If you are customizing and generating
the core in the
Vivado IP integrator, see
Vivado Design Suite User Guide: Designing
IP Subsystems using IP Integrator (UG994) for
detailed information. IP integrator might auto-compute certain
configuration values when validating or generating the design. To
check whether the values do change, see the description of the
parameter in this chapter. To view the parameter value, run the
validate_bd_design command in the Tcl
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
- Select the IP from the IP catalog.
- Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).
The System Cache core parameters are divided into six categories: core, protocol, cache, system, control and ATC. Additionally, when ACE, CCIX or CHI Master Coherency is enabled, the coherency category is also shown, and when CCIX Master Coherency is enabled the SAM category is shown. See the following table for allowed values..
Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.