Only the number of ports specified by
C_NUM_GENERIC_PORTS are available.
There are no registers to read, but basic functionality is tested by writing data and
then reading it back. Output
S<x>_AXI_GEN_AWREADY asserts when the
write address is used,
S<x>_AXI_GEN_WREADY asserts when the write
data is used, and output
S<x>_AXI_GEN_BVALID asserts when the write
response is valid. Output
S<x>_AXI_GEN_ARREADY asserts when the read
address is used, and output
S<x>_AXI_GEN_RVALID asserts when the
read data/response is valid. If the interface is unresponsive, ensure that the following
conditions are met:
ACLKinput is connected and toggling.
- The interface is not being held in reset, and
ARESETNis an active-Low reset.
- Ensure the accessed generic port is activated.
- If the simulation has been run, verify in simulation and/or a Vivado® debugging tool capture that the waveform is correct for accessing the AXI4 interface.