The optional handling of Secure/Non-Secure can be enabled with the
C_ENABLE_NON_SECURE parameter. When active the
AxPROT bit is treated as an extra address bit to provide
a distinction between the two modes. This also means that the same address can be cached
as both Secure and Non-Secure at the same time.
Additional control registers are available when this feature is enabled to allow command and control of the System Cache core, distinguishing between the different modes.