Optimized AXI4 Interfaces - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

Only the number of ports specified by C_NUM_OPTIMIZED_PORTS are available. There are no registers to read, but basic functionality is tested by writing data and then reading it back. Output S<x>_AXI_AWREADY asserts when the write address is used, S<x>_AXI_WREADY asserts when the write data is used, and output S<x>_AXI_BVALID asserts when the write response is valid. Output S<x>_AXI_ARREADY asserts when the read address is used, and output S<x>_AXI_RVALID asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:

  • The ACLK input is connected and toggling.
  • The interface is not being held in reset, and ARESETN is an active-Low reset.
  • Ensure the accessed Optimized port is activated.
  • If the simulation has been run, verify in simulation and/or a Vivado┬« debugging tool capture that the waveform is correct for accessing the AXI4 interface.