The System Cache core is reset by the
ARESETN input signal. ARESETN is synchronous to ACLK and needs
be asserted one ACLK cycle to take affect. The System Cache core is ready for statistic register operation
three ACLK cycles after ARESETN is deasserted. Before the System Cache core is available for general data access the entire memory is
cleared (all previous content is discarded). The time it takes to clear the cache
depends on the configuration; the approximate time is 2*C_CACHE_SIZE/(4*C_CACHE_LINE_LENGTH) clock cycles.
When Address Translation is enabled for the System Cache core, the ATC
table is silently invalidated after reset (all previous content is discarded). The time
it takes to clear the ATC table depends on the configuration; the approximate time is
C_ATC_SIZE+2 (default 258) clock cycles.
The ATC Table can also be silently invalidated in the same way when reset via the System Cache control register, or if the ATS EN field in ATS & PRI Control register changes from Clear to Set.