With Optimized Port Cache Coherency - 5.0 English

System Cache LogiCORE IP Product Guide (PG118)

Document ID
PG118
Release Date
2021-11-05
Version
5.0 English

Optimized port cache coherency enables communication directly from the MicroBlaze™ processor to the System Cache core with sideband information. In this case the MicroBlaze processor code can use the WDC.EXT instructions. There are two types of cache maintenance operations, flush or clear, that can be used depending on how dirty data in the System Cache core for this memory region is handled.

Flush is used when the old data should be retained. This is useful for keeping the old data when the memory region is only partially or sparsely updated from the other master. A flush operation must be used before the other master writes new data or new data might be lost when flushing the system cache. Flush is also used to make sure data written from a MicroBlaze processor is also visible to the other back-door masters.

Clear should be used when the old data is no longer needed or before the entire memory region is completely updated. Clear operations are typically faster than flush because they do not add transactions on the M_AXI interface of the System Cache core, which have the potential of introducing stall conditions depending on utilization level.